JESD403-1C.01
Published: Aug 2024
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages.
Committee(s): JC-45
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SPD4.1.2.L-1
Published: Nov 2013
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 1. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01
Committee(s): JC-45
JESD21-C Solid State Memory Documents Main Page
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