Global Standards for the Microelectronics Industry
MCP and Discrete e•MMC, e•2MMC, and UFS
MCP3.12.1-1
Published: Jun 2024
Item 142.12
This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.
Committee(s): JC-64.2
JESD21-C Solid State Memory Documents Main Page
Free download. Registration or login required.