Global Standards for the Microelectronics Industry
DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1
JESD82-521
Published: Dec 2021
This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K
Committee(s): JC-40.4
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