JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)

JESD319

This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC).

Committee(s): JC-40

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