SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)

JESD255

Published: Mar 2024

The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus.

Committee(s): JC-42, JC-42.4

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