Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE

JESD251-1.01

Published: Sep 2021

This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus  performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018

Committee(s): JC-42.4

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