Global Standards for the Microelectronics Industry
HIGH BANDWIDTH MEMORY (HBM3) DRAM
Published: Jan 2023
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR).
Committee(s): JC-42, JC-42.2
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