Dictionary - Referenced Documents

EIA Standards (EIA and RS*)
RS-308-A* Preparation of Outline Drawings of Solid State Products for JEDEC Type Registration 8/81
RS-311-A* Measurement of Transistor noise Figure and Effective Input Noise Temperature at MF, HF, and VHF 11/81,
Reaffirmed 4/99
RS-323* Air-Convection-Cooled Life Test Environment for Lead-Mounted Semiconductor Devices 3/66,
Reaffirmed 2/72
RS-353* The Measurement of Transistor Noise Figure at Frequencies Up to 20 kHz By Sinusoidal Signal-Generator Method 4/68,
Reaffirmed 4/99
RS-371* The Measurement of Small-Signal VHF-UHF Transistor Short-Circuit Forward Current Transfer Ratio 2/70,
Reaffirmed 4/81
RS-372* The Measurement of Small-Signal VHF-UHF Transistor Admittance Parameters 5/70,
Reaffirmed 4/81
RS-390-A* Standard Test Procedure for Noise Margin Measurements forSemiconductor Logic Gating Microcircuits 2/81
RS-435* Standard for the Measurement of Small-Signal Transistor Scattering Parameters 4/76
EIA-557-A Statistical Process Control Systems 7/95
EIA-599-A National Electronic Process Certification Standard 6/98

* Older EIA standards were identified by the prefix “RS”. While they may still carry that designation on their covers, they are sometimes redesignated (e.g., on the JEDEC Web site) with the prefix “EIA” instead of the prefix “RS”.


Joint Industry Guide, EIA/EICTA/JEDEC/JGPSSI (JIG)
JIG101† Material Composition Declaration for Electronic Products 5/05


JJoint JEDEC/IPC Standards (IPC/JEDEC and J-STD)
IPC/JEDEC-9702 Monotonic Bend Characterization of Board-Level Interconnects 6/04
J-STD-002B Solderability Tests for Component Leads, Terminations, Lugs, Terminals, and Wires 2/03
J-STD-033B† Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices 10/05
J-STD-035 Acoustic Microscopy for Nonhermetic Encapsulated Electronic Components 5/99


JEDEC Publications (JEP)
JEP962 Guidelines for Nondestructive Pull Testing of Wire Bonds on Hybrid Devices 3/77,
Reaffirmed 3/82,
Rescinded 4/00
JEP119A A Procedure for Executing SWEAT 8/03
JEP121A† Requirements for Microelectronic Screening and Test Optimization 10/06
JEP122C† Failure Mechanisms and Models for Semiconductor Devices 3/06
JEP123 Guideline for Measurement of Electronic Package Inductance and Capacitance Model Parameters 10/95
JEP131A† Process Failure Mode and Effects Analysis (FMEA) 5/05
JEP132 Process Characterization Guideline 7/98
JEP133B Guide for the Production and Acquisition of Radiation-Hardness Assured Multichip Modules and Hybrid Microcircuits 3/05
JEP134 Guidelines for Preparing Customer-Supplied Background Information Relating to a Semiconductor-Device Failure Analysis 9/98
JEP136 Signature Analysis 7/99
JEP138 User Guidelines for IR Thermal Imaging Determination of Die Temperature 9/99
JEP140 Beaded Thermocouple Temperature Measurement of Semiconductor Packages 6/02
JEP143A Solid State Reliability Assessment and Qualification Methodologies 5/04
JEP146 Guidelines for Supplier Performance Rating 6/03
JEP148 Reliability Qualification of Semiconductor Devices Based on Physics of Failure Risk and Opportunity Assessment 4/04
JEP149† Application Thermal Derating Methodologies 11/04
JEP150† Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components 5/05


JEDEC Standards (JESD)
JESD4 Definition of External Clearance and Creepage Distances of Discrete Semiconductor Packages for Thyristors and Rectifier Diodes 11/83,
Reaffirmed 1/91
JESD7-A Standard for Description of 54/74HC and 54/74HCT High-Speed CMOS Devices 8/86
JESD10 Low-Frequency Power Transistors 1/76,
Reaffirmed 9/81
JESD12-1B Terms and Definitions for Gate Arrays and Cell-Based Digital ICs 8/93
JESD12-4 Method of Specification of Performance Parameters for CMOS Semicustom ICs 4/87
JESD13-B Standard Specification for Description of ‘B’ Series CMOS Devices 5/80
JESD14 Semiconductor Power Control Modules 11/86,
Reaffirmed 6/92
JESD16-A Assessment of Average Outgoing Quality Levels in Parts per Million (PPM) 4/95
JESD18-A Standard for Description of Fast CMOS TTL-Compatible Logic 1/93
JESD21-C Configurations for Solid State Memories 9/91
JESD22-A105C Power and Temperature Cycling 1/04
JESD22-A108C† Temperature, Bias, and Operating Life 6/05
JESD22-A109-A Hermeticity 7/01
JESD22-A117A† Electrically Erasable Programmable ROM (EEPROM) Program/Erase Endurance and Data Retention Test 3/06
JESD22-A121.01† Measuring Whisker Growth on Tin and Tin Alloy Surface Finishes 10/05
JESD22-B101A† External Visual 10/04
JESD22-B103B Vibration, Variable Frequency 6/02
JESD22-B104C† Mechanical Shock 11/04
JESD22-B108A Coplanarity Test for Surface-Mount Semiconductor Devices 1/03
JESD22-B109 Flip Chip Tensile Pull 6/02
JESD22-B110A† Subassembly Mechanical Shock 11/05
JESD22-B111 Board Level Drop Test Method of Components for Handheld Electronic Products 7/03
JESD22-B112† High-Temperature Package Warpage Measurement Methodology 5/05
JESD22-B113† Board-Level Cyclic Bend Test Method for Interconnect Reliability Characterization of Components for Handheld Electronic Products 3/06
JESD22-B116 Wire Bond Shear Test 7/98
JESD22-B117A† BGA Ball Shear 10/07
JESD22-C101C Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components 12/04
JESD24 Power MOSFETs 7/85
JESD24-1 Method for Measurement of Power Device Turn-Off Switching Loss 9/89
JESD24-2 Gate Charge Test Method 1/91
JESD24-3 Thermal Impedance Measurements for Vertical Power MOSFETs (Delta Source-Drain Voltage Method) 11/90
JESD24-4 Thermal Impedance Measurements for Biploar Transistors (Delta Base-Emitter Voltage Method) 11/90

† This publication was not referenced in previous editions of JESD88 or is a revised edition of a publication that was referenced.