Global Standards for the Microelectronics Industry
Dictionary U
unidirectional-blocking low-capacitance ABD
A two-terminal device that has at least one unidirectional ABD with at least one rectifier p-n junction connected in series in the opposite polarity in order to reduce capacitance.NOTE The unidirectional-blocking low-capacitance ABD is intended to suppress transients in only one direction. The rectifier p-n junction(s) have low capacitance and block in the reverse direction; they are not intended to be operated in their reverse avalanche breakdown regions. The p-n junction that serves as the unidirectional ABD determines which terminal is the anode and which is the cathode; for that determination, the rectifier p-n junction is ignored.
References: JESD77C, 10/09
JESD210, 12/07
unidirectional-conducting low-capacitance ABD
A two-terminal device comprising a unidirectional-blocking low-capacitance ABD and an anti-parallel diode.NOTE To create a low-capacitance ABD with a forward-conducting, low-voltage characteristic, a low-capacitance diode (such as a rectifier) is placed in anti-parallel to the unidirectional-blocking low-capacitance ABD. This diode must have a reverse blocking voltage greater than the avalanche breakdown voltage of the unidirectional ABD.
JESD210, 12/07
unijunction transistor (UJT)
A three-terminal semiconductor device having one junction and a stable negative-resistance characteristic over a wide temperature range.
Graphic symbols (ref. IEEE Std 315):
NOTE In the graphic symbols, the envelope is optional if no element is shown connected to the envelope.
References:JESD77-B, 2/00
unipolar output
An output that, depending on its design, can either source or sink current, but not both.
References:JESD99B, 5/07
unipolar technology
A technology for producing devices in which electrical conduction is due entirely to the flow of majority carriers.
References:JESD77-B, 2/00
JESD99B, 5/07
unit gate size (of a gate array)
A physical space occupied by a single gate equivalent, including any area allocated to power connections, signal connections, and isolation requirements.
References:JESD12-1B, 8/93
JESD99B, 5/07
unit load
A measure of load (usually capacitance) equal to that presented by a specified input of a specified primitive.
References:JESD12-1B, 8/93
JESD99B, 5/07
unit symbol
A letter symbol that is used in place of the name of a unit.
NOTE Neither subscripts nor postscripts may be appended to unit symbols as a means of giving information about the special nature of the quantity under consideration. Such information should be conveyed instead by the quantity symbol.
References:JESD77-B, 2/00
JESD99B, 5/07
universal asynchronous receiver transmitter (UART)
A circuit used in asynchronous data communication applications to provide all the necessary logic to recover data in a serial-in, parallel-out fashion and to transmit data in a parallel-in, serial-out fashion.
NOTE This circuit is usually full-duplex (i.e., it can transmit and receive simultaneously) with the option to handle various data word lengths.
References:JESD100-B, 12/99
universal synchronous receiver transmitter (USRT)
A circuit used in synchronous data communication applications to provide all the necessary logic to recover data in a serial-in, parallel-out fashion and to transmit data in a parallel-in, serial-out fashion.
NOTE This circuit is usually full-duplex (i.e., it can transmit and receive simultaneously) with the option to handle various data word lengths.
References:JESD100-B, 12/99
universal synchronous/asynchronous receiver transmitter (USART)
A circuit used in synchronous/ asynchronous data communication applications to provide all the necessary logic to recover data in a serial-in, parallel-out fashion and to transmit data in a parallel-in, serial-out fashion.
NOTE This circuit is usually full-duplex (i.e., it can transmit and receive simultaneously) with the option to handle various data word lengths.
References:JESD100-B, 12/99
unprotected ESDS device
An electrostatic-discharge-sensitive (ESDS) device that is not in an electrostatic-discharge-protective package.
NOTE See "ESD-protective packing".
References:JESD625-A, 12/99
untestable circuit
A circuit that contains logic functions that cannot be tested because of the lack of controllability or observability.
References:JESD12-1B, 8/93
JESD99B, 5/07
upper byte (U)
An indicator used in conjunction with a data or control term to signify that the combined term applies to the upper byte of a two-byte data interface device; e.g., UW means write enable, upper-byte.
References:JESD21-C, 1/97
upper-byte enable (on word-wide devices) (UB)
An input that, when true, enables the upper byte data input/outputs, terminals DQ8 through DQ15.
References:JESD21-C, 1/97
upper-byte write enable (on word-wide devices) (UW)
An input that, when true, causes the data present on the upper byte input/outputs, terminals DQ8 through DQ15, to be written into the addressed cells of the device.
References:JESD21-C, 1/97
usable gates (in a gate array)
The typical number of gate equivalents that can be used in a given gate array size.
References:JESD12-1B, 8/93
JESD99B, 5/07
USART
See "universal synchronous/asynchronous receiver transmitter".
References:use condition time (tU)
The time interval equivalent to the ELF test duration, as determined by the product of the acceleration factor and the actual accelerated test time: A × tA.
References:JESD74A, 2/07
use conditions
The environmental factors during manufacturing, shipping, and useful life to which a component is exposed.NOTE The useful life consists of the operating, nonoperating, and storage lifetimes.
References: JESD94A, 7/08