Global Standards for the Microelectronics Industry
test mode select (TMS)
A control input that enables the scan test clock and is used to select test modes.References:
(1) A set of test vectors.
(2) A circuit or elements processed in the semiconductor wafer to act as test sites for monitoring fabrication processesReferences:
test port clock (TCK)
Serial scan test clock input.References:
test port reset (TRST)
Serial scan test port resetReferences:
A test pattern and instructions suitable for use on automatic test equipment.
NOTE A test program may be used to perform functional and parametric (ac, dc, or other) tests.References:
The nature of the electrical signal used to measure electrical model parameters. It can be characterized by risetime, pulse shape, frequency, amplitude, etc.References:
test structureA passive metallization structure, including a test line, that is fabricated on a semiconductor wafer by procedures used to manufacture microelectronic integrated devices.
NOTE Connections are provided to make Kelvin-like resistance measurements of the test line, i.e., two taps for sensing voltage when two other terminals force a current through the line. Typically, these terminals are located at the ends of the test line in single-level structures, while multi-level structures have vias that connect the ends of the test line to the over- or underlying metal level in which the terminals are located.References: JESD33B#, 2/04
Creation and insertion of test circuitry to improve testability of a design.References:
A single instance of input stimuli and expected output responses.References:
A circuit or IC designed for the purpose of evaluating one or many device characteristics.
NOTE 1 For the purposes of JESD89, the characterization is the soft-error sensitivity of a particular process technology, but the test vehicle can incorporate other structures used to characterize different parameters, such as yield, speed, voltage margin, etc.
NOTE 2 This test vehicle is not typically a product but is a dedicated component or section of an IC chip designed to be used in predicting the SER of a product.References:
test-pattern fault coverage
The ratio of the total number of detected faults to the total number of detectable faults.References:
tester strobe time
The time interval from the beginning of a test clock cycle to the instant when an output of a device is observed and compared to an expected result.References:
testing of dynamic devices
Latch-up trigger testing of a device in a known stable state, at the minimum-rated clock frequency applied to the device.References:
tetrode field-effect transistor
A field-effect transistor having two independent gate regions, a source region, and a drain region. (Ref. IEC 747‑8.)
NOTE 1 A substrate terminated externally and independently of other elements is considered a gate for the purposes of this definition.
NOTE 2 If no confusion is likely, the term may be abbreviated to "field-effect tetrode."References:
See "test function".References:
thermal impedance, (transient) (Zè, Zθ(t), or Zth) (formerly θ(t))
The change in temperature difference between two specified points or regions that occurs during a time interval divided by the step-function change in power dissipation that occurred at the beginning of the interval and caused the change in temperature difference.References:
thermal impedance, junction-to-ambient (ZèJA, ZθJA(t), or ZthJA) (formerly θJ‑A(t))
The transient thermal impedance from the semiconductor junction(s) to the ambient.References:
thermal impedance, junction-to-case (ZèJC, ZθJC(t), or ZthJC) (formerly θJ‑C(t))
The transient thermal impedance from the semiconductor junction(s) to a stated location on the case.References:
thermal impedance, junction-to-lead (ZèJL or ZthJL)
The transient thermal impedance from the semiconductor junction(s) to a stated location on a lead.References:
thermal impedance, junction-to-mounting-surface (ZèJM or ZthJM)
The transient thermal impedance from the semiconductor junction(s) to a stated location on the mounting surface.References: