Dictionary T

The fractional change in resistance of the test structure per unit change in temperature at a specified temperature T_ref, as described in the following equation:

where

R(T_ref) is the resistance of the test structure at temperature T_ref (Ω);
ΔR is the change in resistance (Ω);
ΔT is the change in temperature that caused the change in resistance (°C).

JEP119A, 8/03
JESD33B#, 2/04
JESD61, 4/97

NOTE 1 The letter symbol for the temperature coefficient of an analog characteristic consists of the letter symbol α with a subscript referring to the relevant characteristic, e.g., a_EG for the temperature coefficient of the gain error.

NOTE 2 Temperature coefficients of analog characteristics are usually specified in "parts per million (relative to the full-scale value) per degree Celsius", that is, in "ppm/^oC".

JESD99B, 5/07

The time interval between one high-temperature extreme and the next, or from one low-temperature extreme and the next.

JESD22-A105C, 1/04

NOTE 1    Derating is usually expressed graphically or in terms of derating factors (e.g., mA/°C or mW/°C).

NOTE 2    For ABDs, derating applies to ratings for peak pulse current (I_PPSM), peak pulse power (P_PPSM), and average power dissipation (P_M(AV)).

NOTE 3    Average power ratings are derated to zero at the maximum-rated junction temperature. Peak pulse power ratings may exceed zero at the maximum-rated junction temperature.

(2) A graphical portrayal of the spatial temperature distribution in an oven.

An electrical parameter of a semiconductor device that varies directly with junction temperature in a linear or very nearly linear fashion.

JESD51-1, 12/95

An externally available point of connection.

NOTE The use of the term "termination" as a synonym is deprecated because that term denotes the external elements connected to the terminal.

(2) (for outline drawing purposes): That part of the package or device used primarily for making an electrical, mechanical, or thermal connection. Examples of terminals are flexible leads, rigid leads, and studs.

JESD10#, 9/81
JESD22-B108A, 1/03
JESD30D, 7/06
JESD77-B, 2/00
JESD99B, 5/07
JESD282-B, 4/00

RS-308-A, 8/81

The terminal that is designated "1" by the manufacturer.

JESD77-B, 2/00

The terminal that is designated "2" by the manufacturer.

JESD77-B, 2/00

The point on the terminal surface that exhibits the greatest perpendicular distance from the package substrate.

JESD22-B108A, 1/03

The term "terminal-to-ground capacitance" is preferred.

JESD99B, 5/07

The measurement of a parameter and the comparison to a standard.

JEP143, 5/04

The test temperature, supply voltage, current limits, voltage limits, clock frequency, input bias voltages, and preconditioning vectors applied to a device being tested.

JESD78A, 2/06

Serial scan test data input.

JESD21-C, 1/97

Serial scan test data output.

JESD21-C, 1/97

The configuration of conductors and dielectrics used to bring test signals to the device under test in a consistent manner.

JEP123, 10/95

On a memory, the input that, when true, causes built-in on-chip test logic to be actuated and the part to go into its test mode of operation.

JESD21-C, 1/97

A metallization line of specified dimensions, with or without vias making connections to over- or underlying metal levels, whose length is defined by the locations of two voltage taps used to make Kelvin-type resistance measurements of the test line when two other terminals force a current through the line.

JESD33B, 2/04

The resistance of the non-joule-heated test line at any time during the test.

JESD61, 4/97

The instructions for executing a test or applying a stress.

JEP143, 5/04