Global Standards for the Microelectronics Industry
Dictionary P
PD(n)
See "presence detect".
References:peak acceleration
The maximum acceleration during the dynamic motion of the test apparatus.
References:JESD22-B111, 7/03
peak junction temperature (TJ (peak))
The highest temperature on the semiconductor chip due to power dissipation internal to the semiconductor chip.
References:JESD51-1, 12/95
peak point (1) (of a programmable unijunction transistor characteristic)
The point on the current-voltage characteristic corresponding to the lowest current at which dvAK/diA = 0 when the gate is biased from a resistive voltage divider.
(2) (of a unijunction transistor characteristic): The point on the emitter current-voltage characteristic corresponding to the lowest current at which dvEB1/diE = 0.
References:JESD77-B, 2/00
JESD77-B, 2/00
peak reflow temperature
The maximum package reflow temperature as specified in J-STD-020, depending on package dimensions and on whether the product is intended for eutectic Sn-Pb or Pb-free reflow soldering.
References:JESD22-B112, 5/05
peak reverse recovery current (IRM(REC))
The maximum instantaneous value of reverse current that occurs when switching from a forward current condition to a reverse voltage condition.
References:JESD41, 5/95
peak-to-peak noise voltage (of a voltage regulator) (VN(PP))
The peak-to-peak output noise voltage with constant load and no input ripples.
References:JESD99B, 5/07
pedestal error (of an analog-to-digital converter or a digital-to-analog converter) (Ep)
A dynamic offset error produced in the commutation process.
References:JESD99B, 5/07
period jitter (tjit(per))
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles.
References:JESD65B, 9/03
peripheral driver
A circuit designed to interface a digital device with an external nondigital device such as a lamp, light-emitting diode, or data bus.
References:JESD99B, 5/07
peripheral equipment
In a data processing system, any equipment, distinct from the central processing unit, that may provide the system with outside communication or additional facilities. (Ref. ANSI X3.172.)
References:JESD100-B, 12/99
peripheral-leaded surface-mount component
A component with a metal frame that provides external surface-mountable terminals located around the periphery of the body of the component.
References:JEP150, 5/05
peristaltic charge-coupled device
Synonym for "buried-channel charge-coupled device".
References:JESD99B, 5/07
phase jitter (tjit(φ))
The deviation in static phase offset, t(φ), for a controlled edge with respect to the mean value of t(φ) in a random sample of cycles.
References:JESD65B, 9/03
phase margin (φm)
The absolute value of the open-loop phase shift between the output and the inverting input at the frequency at which the modulus of the open-loop voltage amplification is unity.
References:JESD99B, 5/07
phase-locked [lock (φ)]
The condition of a phase-locked loop (PLL) device where the reference input and the feedback input remain within the designated static phase offset.
References:JESD65B, 9/03
photoconductive diode
A photodiode that is intended to be used as a photoconductive transducer.
References:JESD77-B, 2/00
