Dictionary P

The process of verifying the specified dc parameters of a device.

JESD12-1B, 8/93
JESD99B, 5/07

A technique for problem-solving in which all potential problem areas or sources of variation are ranked according to their contribution.

EIA-557-A, 7/95
JEP131A, 5/05

The process by which a design is mapped into multiple components or functional blocks within a device.

JESD12-1B, 8/93
JESD99B, 5/07

A statistically based methodology for monitoring that results in the identification and classification of defects using predetermined boundary conditions.

JESD50A, 12/04

Synonym for "bus driver".

JESD99B, 5/07

The formation of an insulating layer directly over a semiconductor surface to protect the surface from contaminants, moisture, and particles.

NOTE Usually an oxide of the semiconductor is used; however, deposition of other materials is also used.

JESD99B, 5/07

See "circuit element, passive".

A device in which all circuit elements are passive.

JESD99B, 5/07

An output similar to an open-circuit except that, in addition to having an internal connection through an active device to a supply voltage, it also has an internal connection through a passive device, usually a resistor, to a second supply voltage that is more negative (less positive) than the first supply voltage.

NOTE According to the state of the active device, the output voltage can swing between levels approaching the two supply voltages.

Graphic symbol (ref. ANSI/IEEE Std 91 and IEC 617‑12):

NOTE The bar above the diamond indicates that the output is at the high logic level when the active device is in its on state.

JESD99B, 5/07

An output similar to an open-circuit output except that, in addition to having an internal connection through an active device to a supply voltage, it also has an internal connection through a passive device, usually a resistor, to a second supply voltage that is more positive (less negative) than the first supply voltage.

NOTE According to the state of the active device, the output voltage can swing between levels approaching the two supply voltages.

Graphic symbol (ref. ANSI/IEEE Std 91 and IEC 617‑12):

NOTE The bar below the diamond indicates that the output is at the low logic level when the active device is in its on state.

JESD99B, 5/07

A category assigned to Pb-free components, boards, and assemblies indicating the general family of material used for the 2^nd‑level interconnect including solder paste, lead/terminal finish, and terminal material or alloy solder balls.

JESD97, 5/04

A label indicating that the enclosed components, devices, and/or board assemblies are considered to be Pb-free as defined in JESD97 and this dictionary.

NOTE This label is not to be applied to items that contain Pb but are exempt according to the RoHS directive.

JESD97, 5/04

A symbol that can be used in place of the phrase "Pb-free".

JESD97, 5/04

Relating to electrical and electronic assemblies and components in which the lead (Pb) level in any of the raw materials and the end product is less than or equal to 0.1% by weight and that also meet the Pb-free requirements/definitions adopted by the RoHS Directive 2002/95/EC.

NOTE The reliability or performance of an assembly or component may be adversely affected by some Pb-free attachment time-temperature profiles; therefore, a time-temperature profile must be selected that will successfully attach the assemblies or components without causing their maximum temperature ratings to be exceeded.

JESD97, 5/04

NOTE    Component and end-product suppliers may desire to clarify this important distinction between 0% and 0.1% lead (Pb) with their customers.

A JEDEC designation for systems with a 133-MHz front-side bus using SDRAM main memory technology, running at a nominal clock frequency of 133 MHz.

JESD82-2, 7/01

See "product or process change notice".

See "soft error, power cycle"