Dictionary P

A suffix that may be added to the names of any additional data pins that may be used as parity bits when these additional pins are allowed by JESD21-C (e.g., DQP).

JESD21-C#, 1/97

See "program or program enable".

See "ball-grid array", "can package", "chip carrier", "chip‑scale package", "clamped package", "die-size package", "disk-button package", "dual‑in‑line package", "flange-mount package", "flatpack", "grid-array package", "in-line module", "in‑line package", "long-form package", "microelectronic assembly", "post-mount package", "press‑fit package", "press-pack", "quad flatpack", "single-in-line package", "small‑outline package", "special-shape package", "stud-mount package", "uncased chip", "vertical surface‑mount package", and "wafer-level package".

An enclosure for one or more semiconductor chips (dice), film elements, or other components, that allows electrical connection and provides mechanical and environmental protection.

JESD99B, 5/07

The physical area available for external electrical and mechanical interfaces.

JESD12-1B, 8/93
JESD99B, 5/07

An area on a chip to which a connection can be made.

JESD99B, 5/07

An integrated circuit whose chip size is determined by the number of pads required.

JESD12-1B, 8/93
JESD99B, 5/07

Synonym for "die-attach pad".

JEP123, 10/95

(1) In virtual memory, a fixed-length block that is transferred as a unit between main storage and auxiliary storage. (Adapted from ANSI X3.172.)

(2) A segment of a memory addressed by a subset of its full address field, usually with speed and/or power benefits relative to access by the full address.

JESD100-B, 12/99

An operating mode in which all accesses to a memory occur within a defined page boundary.

NOTE For example, for a dynamic random-access memory, the page may be defined by the row address with the column addresses entered on the active transitions of the column address strobe. See also "static-column page mode".

JESD100-B, 12/99

The input on a page select memory that, when true, unconditionally causes the page select address register to be reset to zero and the corresponding page to be selected.

JESD21-C, 1/97

The input on a page-select memory that, when true, causes one of the pages of memory to be selected as identified by the inputs on the DQ pins (as defined in the appropriate function table) and also causes this page address to be stored in an internal register.

JESD21-C, 1/97

A processing mode in which operations are performed concurrently in one or more devices. (Ref. ANSI X3.172.)

NOTE Contrast with serial operation.

JESD100-B, 12/99

The simultaneous transmission on separate channels or bus lines of all the bits necessary to complete a clock cycle.

JESD100-B, 12/99

A measurable characteristic.

EIA-557-B#, 2/06
EIA-599-A#, 6/98
JESD659B, 2/07

A macro function produced by a module generator.

JESD12-1B, 8/93
JESD99B, 5/07

A macrocell produced by a module generator.

JESD12-1B, 8/93
JESD99B, 5/07

An out-of-tolerance current or voltage level at an input, output, or power-supply terminal of a component. Parametric failures are usually detected during input-leakage, output-voltage, power-supply-current, timing/switching, and capacitance tests.

JEP134, 9/98

In a circuit, a fault that results in failure to meet ac or dc specifications but does not cause functional failure.

JESD12-5, 8/88