Global Standards for the Microelectronics Industry
Dictionary O
outlier product
Product that meets manufacturer specifications and user requirements but exhibits anomalous characteristics with respect to a normal population (an example of which is depicted by the histogram in the figure), and which may be subject to a higher-than-normal level of failures in the user's application.
LSL = lower spec limit USL = upper spec limit
Example of outlier product
References:JESD62A, 5/02
output buffer
A cell or macro that accepts inputs from cells or macros internal to the integrated circuit and propagates signals external to the integrated circuit.
References:JESD12-4, 4/87
output clamp current (IOK)
An output current in a region of relatively low differential resistance that serves to limit the voltage swing.
References:JESD99B, 5/07
output clamp voltage ( VOK)
An output voltage in a region of relatively low differential resistance that serves to limit the voltage swing.
References:JESD99B, 5/07
output clock (C)
The input that, on some devices containing an output data register, causes the data to be set into the register.
References:JESD21-C, 1/97
output current (IO) (1) (general)
The current into the output terminals.
(2) (of a voltage regulator): Synonym for "load current".
References:JESD14, 11/86
JESD99B, 5/07
output enable (1) (general)
A control input to an integrated circuit that, depending on the logic level applied to it, either permits or prevents the output of data from the device.
NOTE When disabled, the outputs assume a low level, a high level, or a floating (high-impedance) state, depending on the design of the particular circuit.
(2) (of a memory) [pin name G(n); OE(n)]: the input that, when false, disables the outputs and causes them to go to an inactive state but does not affect the writing function.
NOTE When disabled, the inactive state is floating (Z, high-impedance) for MOS and TTL devices, and low (L) for ECL devices. In modules that have multiple OEs, the OEs are numbered beginning with 0.
References:JESD100-B, 12/99
JESD21-C, 1/97
output impedance (of a voltage regulator) (zo)
The small-signal impedance between the regulator output terminal and ground.
References:JESD99B, 5/07
output impedance control (ZQ)
An analog signal input that sets the output buffer impedance and the operating mode.
References:JESD21-C, 1/97
output impedance, differential (zod)
The small-signal impedance between two ungrounded output terminals of a differential amplifier.
References:JESD99B, 5/07
output impedance, single-ended (zos)
The small-signal impedance between one output terminal of a differential amplifier and ground with the other output terminal ac-grounded.
References:JESD99B, 5/07
output load
The load on an output (usually specified in unit loads).
References:JESD12-1B, 8/93
JESD99B, 5/07
output noise voltage (of a voltage regulator) (Vn)
The rms output noise voltage with constant load and no input ripples.
References:JESD99B, 5/07
output offset voltage (VOO)
The dc voltage between two output terminals (or the output terminal and ground for circuits with one output) when the input terminal(s) are grounded.
References:JESD99B, 5/07
output pin
A device pin that generates a signal or voltage level as a normal function during the normal operation of the device.
NOTE Output pins, though left in an open (floating) state during testing of other pin types, are latch-up tested.
References:JESD78A, 2/06
output resistance (ro)
The small-signal resistance between an output terminal and ground or between differential output terminals.
References:JESD99B, 5/07
output stage drain power voltage (VDDQ)
The power pin that is intended to supply power to the output transistors of the device to provide the potential and energy to drive the load applied to the data output (Q) pins or data input/output (DQ) pins. Other, non-data, output transistors may also be designated to be supplied by this power pin. The potential of VDDQ may be specified the same as or different from that of the primary device power pins (VDD).
References:JESD21-C#, 1/97
output stage logic power voltage (VCCQ)
The power pin that is intended to supply power to the output transistors of the device to provide the potential and energy to drive the load applied to the data output (Q) pins or data input/output (DQ) pins. Other, non-data, output transistors may also be designated to be supplied by this power pin. The potential of VCCQ may be specified the same as or different from that of the primary device power pins (VCC). VCCQ is restricted to 5‑V applications only.
References:JESD21-C#, 1/97
output stage source power voltage or output stage ground reference (pin) (VSSQ; GNDQ)
The ground reference voltage for the data output (Q) or input/output (DQ) pins. Other, non-data, output transistors may also be designated to be referenced to this ground pin. Internal to the device, this pin shall be dc-isolated from the primary ground reference (VSS) pin and any other ground reference pin. External to the device, it must be dc‑common with the primary ground reference.
References:JESD21-C, 1/97
