Dictionary L

See "latch enable".

See "lower byte".

See "lot acceptance rate".

The ratio, usually expressed in dB, of the signal power delivered to the load to the large-signal power delivered to the input.

JESD10, 9/81

The product of the large-signal ac output current and voltage in the common-emitter circuit configuration.

JESD10, 9/81

Synonym for "pushdown storage".

JESD100-B, 12/99

On devices containing a latch register, an input that causes the data to be latched into the register

JESD21-C, 1/97

A state in which a low-impedance path, resulting from an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the triggering condition.

NOTE 1 The overstress can be a voltage or current surge, an excessive rate of change of current or voltage, or any other abnormal condition that causes the parasitic thyristor structure to become regenerative.

NOTE 2 Latch-up will not damage the device provided that the current through the low-impedance path is sufficiently limited in magnitude or duration.

JESD78A, 2/06
JESD99B, 5/07

A condition in which a regulator has been driven into the foldback limiting mode and will not respond to the removal of the overload.

JESD99B, 5/07

A PROM that contains a latch register for the output data.

JESD21-C, 1/97

A surface region of a semiconductor device whose conductivity type is the same as that produced by the net fixed charge density of ionized donors and acceptors and whose net carrier density is higher than that necessary for neutralization due to charge carrier attraction.

NOTE The charge carrier attraction may be caused by a field-plate voltage such as in field-effect transistors or by unwanted charge residing in surface states, insulating layers, or surface ionic species.

JESD99B, 5/07

A distinguishable region introduced under a semiconductor circuit element, for example, under the collector region of a transistor to reduce the series collector resistance.

JESD99B, 5/07

A region whose conductivity type on each side of the junction is the same as that produced by the net fixed charged density of ionized donors and acceptors but whose net carrier density is insufficient for neutralization due to the built-in potential barrier of the p-n junction and, if present, an applied reverse bias.

(2) (associated with a surface): A surface region of a semiconductor device whose conductivity type is the same as that produced by the net fixed charge density of ionized donors and acceptors but whose net carrier density is insufficient for neutralization due to charge carrier attraction.

NOTE The charge carrier attraction may be caused by a field-plate voltage such as in field-effect transistors or by unwanted charge residing in surface states, insulating layers, or surface ionic species.

JESD99B, 5/07

The region of a semiconductor into which impurity dopants have been diffused to a concentration of at least the background concentration.

NOTE The region is often delineated by a p-n junction.

JESD99B, 5/07

Synonym for "accumulation layer".

JESD99B, 5/07

A surface region of a semiconductor device whose conductivity type has been reversed from that produced by the net fixed charge density of ionized donors and acceptors due to charge carrier attraction.

NOTE The charge carrier attraction may be caused by a field-plate voltage such as in field-effect transistors or by unwanted charge residing in surface states, insulating layers, or surface ionic species.

JESD99B, 5/07

See "lower byte enable".

See "linear burst order".