Global Standards for the Microelectronics Industry
Dictionary G
G
See "giga (as a prefix to units of semiconductor storage capacity)".
References:G(n)
See "output enable".
References:G; g
See "gate terminal".
References:gain error (of a linear analog-to-digital converter [digital-to-analog converter]) (EG)
The difference between the actual midstep [step] value and the nominal midstep [step] value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero.
NOTE 1 The terms "gain error" and "offset error" should be used only for errors that can be adjusted to zero. Otherwise, the terms "zero-scale error" and "full-scale error" should be used.
NOTE 2 Usually the specified steps for the specification of gain error and offset error are the steps at the end of the practical full-scale range.
NOTE 3 The midstep value of a step is defined (for an analog-to-digital converter) as the value for a point ½ LSB apart from the adjacent transition.
References:JESD99B, 5/07
gain point (of an adjustable analog-to-digital converter [digital-to-analog converter])
The point in the transfer diagram corresponding to the midstep [step] value of the step for which gain error is specified (usually full scale), and in reference to which the gain adjustment is performed.
NOTE Gain adjustment causes only a change of the slope of the transfer diagram, without changing the offset error.
References:JESD99B, 5/07
gate
The electrode associated with the region in which the electric field due to the control voltage is effective.
References:JESD24, 7/85
gate array integrated circuit
A digital integrated circuit containing a fixed topology of circuit elements used to form macrocells and macro functions that are or can be interconnected to implement a logic function.
References:JESD12-1B, 8/93
JESD99B, 5/07
gate capacity (of a gate array)
Synonym for "usable gates".
References:JESD12-1B, 8/93
JESD99B, 5/07
gate core area (of a cell-based integrated circuit)
The physical area occupied by the logic gates and intercell routing excluding the pad cell area.
References:JESD12-1B, 8/93
JESD99B, 5/07
gate core area (of a gate array)
The physical area occupied by the available logic gates and intercell routing excluding the pad cell area.
References:JESD12-1B, 8/93
JESD99B, 5/07
gate core density (1) (of a cell-based integrated circuit)
The number of gates in the gate core area divided by the gate core area.
NOTE Units are gates per unit area.
(2) (of a gate array): The number of available gates in the gate core area divided by the gate core area.
NOTE Units are gates per unit area.
References:JESD12-1B, 8/93
JESD99B, 5/07
gate current (of a thyristor)
The (control) current into the gate terminal.
References:JESD77-B, 2/00
gate current, dc (IG)
The direct current into the gate terminal.
References:JESD24, 7/85
JESD60A, 9/04
JESD90, 11/04
gate equivalency of a function (GEF)
The number of gate equivalents used to implement a function.
References:JESD12-1B, 8/93
JESD99B, 5/07
gate equivalent (1) (for CMOS)
The minimum circuitry necessary to implement a two-input NAND gate.
(2) (for ECL): One-eleventh of the minimum circuitry necessary to implement a single-bit full-adder.
References:JESD12-1B, 8/93
JESD99B, 5/07
gate plateau voltage (Vgs(pl))
The gate-source voltage when dVgs/dt first reaches a minimum during the turn-on switching transition, for a constant-gate-current drive condition. During turn-off, it is the gate-source voltage at the last minimum dVgs/dt observed.
Gate plateau voltage
References:JESD24-2, 1/91
gate region (1) (of an IGFET)
A control region that determines the surface charge-carrier concentration in the channel region as a function of the gate voltage.
NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.
(2) (of a JFET): A control region that determines the cross-sectional area of the channel region as a function of the gate voltage.
NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.
(3) (of a thyristor): A control region in which a momentary injection of controlling charge causes a regenerative turn-on action.
NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.
References:JESD77-B, 2/00
JESD77-B, 2/00
JESD77-B, 2/00
gate terminal (G, g) (1) (of a field-effect transistor)
The specified externally available point of connection to the gate region.
(2) (of a programmable unijunction transistor): The terminal whose bias conditions determine the values of the unijunction characteristics.
(3) (of a thyristor): The terminal unique to the control circuit.
References:JESD77-B, 2/00
JESD77-B, 2/00
JESD77-B, 2/00
gate utilization (in a gate array)
The ratio of the number of used gates to available gates.
NOTE Gate utilization is usually expressed as a percentage.
References:JESD12-1B, 8/93
JESD99B, 5/07
gate, (logic)
A combinational logic function consisting of a number of inputs and outputs and performing one of the Boolean functions AND, OR, exclusive OR, NAND, NOR, or exclusive NOR.
NOTE For the purpose of specifying complexity, (1) buffers and inverters are counted as gates and (2) exclusive OR and exclusive NOR gates, some high-input-count gates, and memory functions are counted as multiple gates.
References:JESD12-1B#, 8/93
JESD99B, 5/07
