Dictionary E

(1) A region from which charge carriers that will become minority carriers in the base are injected into the base. (Ref. 60 IRE 28.S1.)

(2) The physical region that is designed by the manufacturer to contain the supply region in the normal operating mode and, in a simple discrete transistor, is externally accessible by the designated emitter terminal.

JESD10, 9/81

JESD77-B, 2/00

A supply region that delivers principal-current charge carriers into a controlling base region through an associated emitting junction.

NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal. In the normal operating mode, this functional region is located in the emitter region; in the inverse operating mode, it is located in the collector region.

JESD77-B, 2/00

The specified externally available point of connection to the emitter region.

JESD77-B, 2/00

The dc voltage between the emitter terminal and the base terminal with the collector terminal open-circuited.

JESD10, 9/81

A semiconductor junction in an operating condition in which the net flow of charge carriers of each type across the junction is in the direction from the region where they are majority carriers to the region where they are minority carriers, i.e., in the direction opposite to the force resulting from the internal electric field.

JESD77-B, 2/00

A condition in which there is no bias charge or low-level charge.

JESD99B, 5/07

The time interval between the transition of the enabling signal and the commencement of the intended operation.

JESD100-B, 12/99

The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to the defined high level.

NOTE 1 See note 1 to "disable time from the high level …".

NOTE 2 Because H-type open-circuit outputs are used with pull-down components that cause the outputs to go low when the outputs are turned off, the term "low-to-high-level propagation time" and the symbol t_PLH are frequently used with these outputs for this parameter.

JESD99B, 5/07

The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to the defined low level.

NOTE 1 See note 1 to "disable time from the high level …".

NOTE 2 Because L-type open-circuit outputs are used with pull-up components that cause the outputs to go high when the outputs are turned off, the term "high-to-low-level propagation time" and the symbol t_PHL are frequently used with these outputs for this parameter.

JESD99B, 5/07

The time interval between the transition of the enabling signal and the instant when the supply current has increased from its standby value to its active value.

NOTE This interval is defined with respect to specified reference points on the chip-enable and supply-current waveforms.

JESD100B.01, 12/02

The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to either of the defined active levels (high or low).

JESD99B, 5/07
JESD100-B, 12/99

The transition time between specified reference points on the output voltage waveform with the output changing from a high-impedance (off) state to the defined high level.

NOTE 1 See note 1 to "disable time from the high level …".

NOTE 2 Because H-type open-circuit outputs are used with pull-down components that cause the outputs to go low when the outputs are turned off, the term "low-to-high-level transition time" and the symbol t_TLH are frequently used with these outputs for this parameter.

JESD99B, 5/07

The transition time between specified reference points on the output voltage waveform with the output changing from a high-impedance (off) state to the defined low level.

NOTE 1 See note 1 to "disable time from the high level …".

NOTE 2 Because L-type open-circuit outputs are used with pull-up components that cause the outputs to go high when the outputs are turned off, the term "high-to-low-level transition time" and the symbol t_THL are frequently used with these outputs for this parameter.

JESD99B, 5/07

A network or system in which only one input is excited at a time and each input produces a unique combination of output signals. (Ref. ANSI/IEEE Std 100.)

JESD99B, 5/07

A parameter that characterizes the product (e.g., piece parts, subassemblies, and/or assemblies) at the finished product stage.

EIA-599-A, 6/98

The loss of the ability of a component, as a result of endurance cycling, to meet the electrical or physical performance specifications that (by design or testing) it was intended to meet.

JESD22-A117A, 3/06

The characteristic of a device that exhibits an enhanced total dose response at dose rates below 50 rad(Si)/s.

JEP133B, 3/05

The operation of a field-effect transistor such that changing the gate-source voltage from zero to a finite value increases the magnitude of the drain current. (Ref. IEC 747‑8.)

JESD77-B, 2/00

The operation of a field-effect transistor such that changing the gate-source voltage from zero to a finite value increases the magnitude of the drain current.

JESD24, 7/85