Dictionary D

DT/OE(n)

See "data-transfer/output-enable input"

References:

dual-gate field-effect transistor

Synonym for "tetrode field-effect transistor".

References:

JESD24, 7/85
JESD77-B, 2/00

dual-in-line memory module (DIMM)

A packaging arrangement of memory devices on a socketable substrate.

References:

JESD206, 1/07

dual-in-line package (DIP)

A device package configuration that has two parallel rows of pins that are spaced nominally 0.3 inch, 0.4 inch, or 0.6 inch apart with the pins on 0.1-inch centers.

NOTE See also "in-line package".

References:

JESD21-C, 1/97

dual-port memory (DPM)

Any memory that has two essentially identical data ports.

References:

JESD21-C, 1/97

dual-port static RAM (DPSRAM)

A static RAM that contains two sets of identical random-access address and data ports.

References:

JESD21-C, 1/97

duplex transmission

Data transmission in both directions simultaneously. (Ref. ANSI X3.172.)

References:

JESD100-B, 12/99

DUT

Device under test.

References:

JESD24-8, 8/92
JESD51-1, 12/95
JESD57, 12/96
JESD78A, 2/06
JESD89A, 10/06
JESD89-2, 11/04
JESD89-3, 9/05

duty cycle jitter (tjit(duty))

The magnitude of the deviation in time duration between the primary threshold crossing and the secondary threshold crossing in a cycle over a random sample of cycles.

References:

JESD65B, 9/03

duty cycle, power

The ratio of the power-on time duration per cycle to the total cycle time.

NOTE Power duty cycle is usually expressed as a percentage.

References:

JESD22-A105C, 1/04

DV

See "design validation/verification".

References:

dynamic (read/write) memory

A volatile read/write memory in which the cells require the repetitive application of control signals generated inside or outside the integrated circuit to retain stored data. (Adapted from IEC 748‑2.)

NOTE 1 The words "read/write" may be omitted from the term when no misunderstanding is likely.

NOTE 2 Each repetitive application of the control signals is normally called a refresh operation or cycle.

NOTE 3 A dynamic memory can use static addressing or sensing circuits.

NOTE 4 Contrast with "static (read/write) memory".

References:

JESD100-B, 12/99

dynamic phase offset (t(φ)dyn)

The incremental phase offset between the input reference clock and the feedback input signal of a phase-locked loop (PLL) resulting from modulation of the input reference clock.

References:

JESD65B, 9/03

dynamic random-access memory (DRAM)

A dynamic memory that permits access to any of its address locations in any desired sequence with similar access time to each location.

References:

JESD21-C, 1/97
JESD100B.01, 12/02

dynamic range (of a charge-transfer device)

The range of useful linear operation expressed as the ratio of the saturation input signal to the noise equivalent signal.

References:

JESD99B, 5/07

Pages

Browse Alphabetically

A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z

Document Information

Standards & Documents Assistance:

Published JEDEC documents on this website are self-service and searchable directly from the homepage by keyword or document number. 

Click here for website or account help.

To report potential errors or make suggestions for improvement to a published JEDEC standard, please use this form.  JEDEC does not accept requests for implementation assistance or interpretation of documents. For other inquiries related to standards & documents email Angie Steigleman.

Dictionary RSS Feed

Subscribe to the JEDEC Dictionary RSS Feed to receive updates when new dictionary entries are added.