Dictionary D

data-retention supply voltage (of an SRAM offering a data-retention mode) (VCC(DR), VDD(DR), etc.)

The supply voltage in the data-retention mode.

References:

JESD99B, 5/07

data-retention time

Synonym for "retention time".

References:

JESD100-B, 12/99

data-transfer/output-enable input [DT/OE(n), TRG(n)]

The input of a device having both serial and parallel access ports that, depending on the state of one or more of the other control lines of the device, either enables an internal data transfer between the serial and parallel port circuitry or enables the data outputs of the parallel port.

References:

JESD21-C, 1/97

datum

A theoretically exact point, axis, or plane that is established by tooling and is used in conjunction with a datum feature. The location or geometric characteristics of features of a part are established in relation to the datum.

References:

JESD95-1, 3/97

datum feature

The physical portion of a part that, in conjunction with suitable tooling, establishes the datum.

NOTE A centerline, by itself, cannot be a datum. It must be the centerline of a physical feature such as a hole or boss, etc. In these cases, it is the diameter of the hole or the width of the boss that is designated as the datum. The point of reference is the centerline of these physical features.

References:

JESD95-1, 3/97

DC

See "diagnostic clock".

References:

dc controller

A circuit that produces, from a dc input, a dc output that is proportional to a control input.

References:

JESD14#, 11/86

dc noise margin

The maximum dc voltage amplitude of extraneous signal that can be algebraically added to the noise-free worst-case input level without causing the output voltage to deviate from the allowable logic voltage level.

References:

RS-390-A, 2/81

dc power dissipation (PD)

The total dc power supplied to a device less any power delivered from the device to a load.

References:

JESD99B, 5/07

dc terminal

A terminal that is to be connected to a dc circuit.

References:

JESD14, 11/86

dc test

A test during which only steady-state voltages and currents are applied to the device.

NOTE DC tests are generally used to determine input levels, output levels, or dissipation characteristics of devices.

References:

JESD99B, 5/07

dc trigger point (on the gate characteristic of a thyristor)

The point on the gate characteristic VFG = f(IFG) at which, for continuously rising gate current or gate voltage, the thyristor switches from the off state to the on state.

References:

JESD77-B, 2/00

decade

The interval between two frequencies that have a ratio of 10 to 1. NOTE The number of decades, D, between two frequencies, f1 and f2, is given by D =

References:

log (f2/f1)

decoder

A matrix of logic elements that selects one or more output channels according to the combination of input signals present. (Ref. ANSI/IEEE Std 100.)

References:

JESD99B, 5/07

defect

A localized imperfection or deviation from the designed construction that affects function.

References:

JEP148, 4/04

defect density

The number of defects on a chip divided by its area.

References:

JEP148, 4/04

defect, (physical)

A physical anomaly that adversely affects function or performance. References:

JEP143B.01, 6/08

degradation defect

A physical defect created by the natural changes in the properties of materials over time that is manifested after some period of operation. References:

JEP143B.01, 6/08

delamination

A failure found during tensile pull of flip chip solder joints, where the solder bump interconnection metallization is at least partially removed from either the substrate or the die, with the solder bump remaining continuous.

References:

JESD22-B109, 6/02

delay time (1) (general) (td)

The time interval between a reference point on one waveform and a reference point on another waveform.

(2) (between input and output): The time interval between a transition at an input and a resultant change at an output.

(3) (of an integrated circuit) (td, tdr, and tdf): The time interval between a step-function change of the input signal level and the instant at which the magnitude of the output signal passes through a specified value (normally 10% for tdr or 90% for tdf) close to its initial value. (Ref. IEC 748‑3.)

(4) (of a transistor) (td): (A) The time interval from the point at which the leading edge of the input pulse has reached 10% of its maximum amplitude to the point at which the leading edge of the output pulse has reached 10% of its maximum amplitude.

(B) Synonym for "current delay time, tdi".

References:

JESD77-B, 2/00
JESD99B, 5/07
JESD100-B, 12/99

JESD77-B, 2/00

JESD99B, 5/07

JESD10, 9/81

JESD77-B, 2/00

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