Dictionary B

The overall combination of base region, base terminal, and the interface between them.

NOTE This term should be used in this manner only when no confusion is likely to occur.

JESD77-B, 2/00

The part of a package that includes the surface on which a chip is intended to be mounted.

JESD99B, 5/07

NOTE    A prepreg is a sheet of material that has been impregnated with a resin cured to an intermediate stage (Ref. IPC-T-50).

A metal alloy residing beneath all surface finish(es) and/or underplate.

JESD201, 3/06

A plane parallel to the seating plane through the lowest point on the body of the package. It may coincide with the seating plane.

RS-308-A, 8/81

A region of a semiconductor device into which majority carriers are injected.

JESD77-B, 2/00

(1) A region that lies between an emitter and a collector of a transistor and into which minority carriers are injected. (Ref. 60 IRE 28.S1.)

(2) The physical region that is located between the collector junction and the emitter junction and contains the control region

JESD10, 9/81

JESD77-B, 2/00

A control region through which the principal current passes and in which the concentration of principal-current charge carriers is the result of an applied base current.

NOTE 1 The principal current is the result of diffusion and impurity concentration gradient drift.

NOTE 2 This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.

JESD77-B, 2/00

The specified externally available point of connection to the base region.

JESD77-B, 2/00

See "saturation voltage, base-emitter".

A numerical value used to describe the theoretically exact size, profile, orientation, or location of a feature or datum target. Permissible variations from the basic dimension are established by tolerances on associated dimensions, in notes, or in feature control frames.

JESD95-1, 3/97

A plot of failure rate versus time or cycles that exhibits three phases of life: infant mortality (initially decreasing failure rate), intrinsic or useful life (relatively constant failure rate), and wear-out (increasing failure rate).

JESD74A, 2/07
JESD85, 7/01
JESD91A, 8/01

The signals BD1 and BD2 generated by the memory card as an indication of the condition of the battery on the memory card. Both signals are kept asserted when the battery is in good condition. When BD2 is negated while BD1 is still asserted, the battery is in a warning condition and should be replaced, although data integrity on the card is still assured. If BD1 is negated with BD2 either asserted or negated, the battery is no longer serviceable and data is lost.

JESD21-C, 1/97

A unit of signaling speed equal to the number of discrete conditions or signal events per second. (Ref. ANSI X3.172.)

NOTE For example, one baud equals one bit per second in a train of binary signals or one 3‑bit value per second in a train of signals each of which can assume one of eight (2³) different states.

JESD100B.01, 12/02

See "bucket-brigade device".

See "buried-channel charge-coupled device".

See "bipolar-and-CMOS-and-DMOS technology".

A BiCMOS series that includes devices whose input logic levels are TTL-compatible and whose outputs are specified at TTL levels; the low-level output voltage is specified at 24 mA and 48 mA.

JESD54#, 2/96

See "battery voltage detect".

See "burst DRAM".