Recently Published Documents

Title Document # Date Details
Annex D, Raw Card D, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card D, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These DDR4 SO-DIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.60.

MODULE4.20.25.D Mar 2022 view
TEMPERATURE RANGE AND MEASUREMENTS FOR COMPONENTS AND MODULES

This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Items 1855.13, 1855.16, 1855.22, and 1855.24

JESD402-1A Mar 2022 view
Registration - Plastic Dual Small Outline Surface, 2 Terminal, Wettable Flank Package

Designator: PDSO-N2-I#-R#x#Z#-CturET0p04 Item: 11.11-1000, Access STP File for MO-343B  Cross Reference: DG4.20 

MO-343B Mar 2022 view
Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04 
Item: 11.11-999, Access STP Files for MO-340
Cross Reference: DR4.8, DR4.16, DR4.20

MO-340C Mar 2022 view
Registration - Plastic Dual Connector

Designator: PDXC-PP2-I8p9-R107p6xp15Z26p0-DD2p95x1p1 
Item: 11.14-208, Access STP Files for SO-025B
Cross Reference: TBD

SO-025B Mar 2022 view
Registration - Enclosure Form Factor for Automotive SSD Connector, Board Mount

Designator: PBCX-K4_... 
Item: 11.14-211,  Access STP Files for SO-030A

Cross Reference: MO-348

SO-030A Feb 2022 view
Registration - 262 Pin DDR5 SODIMM, 0.50 mm Pitch Package

Designator: PDMA-N262-I0p5-R69p6x3p7Z30p15R2p55x02p35 Item: 11.14-207, Access STP Files for MO-337B Cross Reference: SO-024

MO-337B Feb 2022 view
Registration - 288 Pin DDR5 DIMM, 0.85 mm Pitch Microelectronic Assembly

Designator: PDMA-N288-I0p85-R133p8x#p#7Z31p8R2p55x0p6
Item: 11.14-212, Access STP Files for MO-329E
Cross Reference: MO-329, SO-023, GS-010

MO-329E Jan 2022 view
DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Specification

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM) and Load Reduced (LRDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These 288-pin Registered and Load Reduced DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments. Item 2273.07.

JESD305 Jan 2022 view
TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES

This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow.

JESD22-A120C Jan 2022 view
Registration - Enclosure Form Factor for Automotive SSD Connector, Cable Mount

Designator: PBXC-K4_D#p##-MR36p05x14p5Z10p25-HS 
Item: 11.14-210, Access STP Files for SO-029A

Cross Reference: MO-348

SO-029A Jan 2022 view
Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices

This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons.

*This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications.

 

JEP151A Jan 2022 view
SERIAL INTERFACE FOR DATA CONVERTERS

This is a minor editorial change to JESD204C, the details can be found in Annex A. This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this document. Informative sections are included to clarify and exemplify the standard. Item 192.02B.

JESD204C.01 Jan 2022 view
DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1

This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K

JESD82-521 Dec 2021 view
Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0

This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained.

JEP186 Dec 2021 view
Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets

This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets.

JEP187 Dec 2021 view
Backup Energy Module Standard for NVDIMM Memory Devices (BEM)

This standard defines the functional requirements of Backup Energy Module (BEM), henceforth referred to as BEM in this standard. This module shall be used to provide backup power to the Industry Defined Storage Array Controller Cards and NVDIMM-n as applicable. All standards are applicable under all operating conditions unless otherwise stated. Item 2279.03

JESD315 Dec 2021 view
Registration - Plastic Bottom Grid Array Ball, 0.35 mm x 0.40 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p35...Item 11-998

MO-350A Nov 2021 view
SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTION

This inspection method is for product semiconductor wafers and dice prior to assembly. This test method defines the requirements to execute a standardized external visual inspection and is a non-invasive and nondestructive examination that can be used for qualification, quality monitoring, and lot acceptance.

JESD22-B118A Nov 2021 view
NAND FLASH INTERFACE INTEROPERABILITY

This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations.

JESD230F Oct 2021 view
DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document.

JESD82-10A.01 Oct 2021 view
DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. This is a minor editor revision as shown in Annex A of the document.

JESD82-19A.01 Oct 2021 view
Registration - Shipping and Handling Tray for DDR5 DIMM Microelectronic Assembly

Designator: N/A
Item: 11.5-997, Access STP Files for CO-036B
Cross Reference: N/A

CO-036B Oct 2021 view
REGISTRATION - Battery Cell R/A T/H Type Connector, 1.2 mm Pitch

Designator: PSXC-P6_I1p2-R11p6x5p85Z2p0-R0p3x0p31H1p16
Item: 11.14-198, Access STP Files for SO-026A
Cross Reference: N/A

SO-026A Oct 2021 view
REGISTRATION - Battery Cell R/A SMT Type Connector, 1.2 mm Pitch

Designator: PSXC-L6_I1p2-R11p6x5p85Z2p07-R0p3x0p6ET0p07
Item: 11.14-198, Access STP Files for SO-028A
Cross Reference: N/A

SO-028A Oct 2021 view
DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. SSTU32S2868 denotes a single-die implementation and SSTU32D868 denotes a dual-die implementation. This is a minor editorial revision as shown in Annex A of the document.

JESD82-14A.01 Oct 2021 view
DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document.

JESD82-16A.01 Oct 2021 view
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document.

JESD82-4B.01 Oct 2021 view
DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

This standard provides the functional definition, ball-out configuration and package outline, signal definitions and input/output characteristics for a 28-bit 1:2 registered driver with parity suitable for use on DDR2 RDIMMs. The SSTU32865 integrates the functional equivalent of two SSTU32864 devices (as defined in JESD82-7) into a single device, thereby easing layout and board design constraints especially on high density RDIMMs such as dual rank, by four configurations. Moreover, the optional use of a parity function is provided for, permitting detection and reporting of parity errors across its 22 data inputs. JESD82-9 specifies a 160-pin Thin-profile, fine-pitch ball-grid array (TFBGA) package. This is a minor editorial revision as shown in Annex A of the document.

JESD82-9B.01 Oct 2021 view
Registration - Battery Cell Wire Side Connector, 1.2 mm pitch

Designator: PBXC-q6_i1P2-r7P9X4P25z1P58Item: 11.14-199, Access STP Files for SO-027ACross Reference: N/A

SO-027A Sep 2021 view
TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE

This test is used to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g., flip-flops) by measuring the error rate while the device is irradiated in a neutron or proton beam of known flux. The results of this accelerated test can be used to estimate the terrestrial cosmic ray induced SER for a given terrestrial cosmic ray radiation environment. This test cannot be used to project alpha-particle induced SER.

JESD89-3B Sep 2021 view
MEASUREMENT AND REPORTING OF ALPHA PARTICLE AND TERRESTRIAL COSMIC RAY INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES

This specification defines the standard requirements and procedures for terrestrial soft-error-rate (SER) testing of integrated circuits and reporting of results. Both real-time (unaccelerated) and accelerated testing procedures are described. At terrestrial, Earth-based altitudes, the predominant sources of radiation include both cosmic-ray radiation and alpha-particle radiation from radioisotopic impurities in the package and chip materials. An overall assessment of a deviceís SER is complete, only when an unaccelerated test is done, or accelerated SER data for the alpha-particle component and the cosmic-radiation component has been obtained.

JESD89B Sep 2021 view
Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE

This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus  performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018

JESD251-1.01 Sep 2021 view
Registration - Plastic, Ultra, Extra and Super Thin, Fine Pitch, Dual Small Outline, Flat, Leaded Package. (U, X1, X2)F-PSOF, HX2-PSOF.

Item 11.10-459

MO-293B Sep 2021 view
DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD01)

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD01 Device ID is DID = 0x0051.

JESD82-511 Aug 2021 view
ENCLOSURE FORM FACTOR FOR SSD DEVICES, VERSION 1.0

This document specifies the enclosure form factor which can be used with various type of SSD devices: outline of the top and bottom enclosure, three screw holes to mount the enclosure on the system, and two clamping holes in the top enclosure to lock to the connector. Item 318.06. This is a minor editorial revision detailed in Annex D.

JESD253.01 Aug 2021 view
GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES

This standard identifies the general requirements for Distributors that supply Commercial and Military products. This standard applies to all discrete semiconductors, integrated circuits and Hybrids, whether packaged or in wafer/die form, manufactured by all Manufacturers. The requirements defined within this document are only applicable to products for which ownership remains with the Distributor or Manufacturer.

JESD31F Aug 2021 view
XFM DEVICE, Version 1.0

This standard specifies the mechanical and electrical characteristics of the XFM Device. Such characteristics include, among others, package dimensions, pin layout, signal assignment, power supply voltages, currents, and electrical characteristics of the PCIe interface.

JESD233 Aug 2021 view
COPY-EXACT PROCESS FOR MANUFACTURING

This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements.

JEP185 Aug 2021 view
TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE

This test method is offered as standardized procedure to determine the alpha particle Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flipflops) by measuring the error rate while the device is irradiated by a characterized, solid alph source.

JESD89-2B Jul 2021 view
TEST METHOD FOR REAL-TIME SOFT ERROR RATE

This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources.

JESD89-1B Jul 2021 view

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