Global Standards for the Microelectronics Industry
Recently Published Documents
Title | Document # | Date | Details |
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HIGH BANDWIDTH MEMORY (HBM3) DRAM The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). |
JESD238A | Jan 2023 | view |
SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS This publication is a guideline to assist manufacturers of integrated circuits in defining conditions for burn-in and life test of their products to meet quality and reliability performance requirements of MIL-PRF-38535. |
JEP163A | Jan 2023 | view |
Guidelines for Gate Charge (QG) Test Method for SiC MOSFET This publication defines a QGS, TOT, QGD and QGS, TH which can be extracted from a measured QG waveform for SiC MOSFETs. |
JEP192 | Jan 2023 | view |
Survey On Latch-Up Testing Practices and Recommendations for Improvements This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. |
JEP193 | Jan 2023 | view |
THERMAL SHOCK This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. |
JESD22-A106B.02 | Jan 2023 | view |
JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices This method provides users with an acoustic microscopy process flow for detecting anomalies (delaminations, cracks, mold compound voids, etc.) nondestructively in encapsulated electronic devices while achieving reproducibility. |
J-STD-035A | Dec 2022 | view |
JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs) The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. |
J-STD-020F | Dec 2022 | view |
PROCESS CHARACTERIZATION GUIDELINE This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool. |
JEP132A.01 | Dec 2022 | view |
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. |
JESD47L | Dec 2022 | view |
Secure Serial Flash Bus Transactions This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure. |
JESD254 | Dec 2022 | view |
GUIDELINES FOR COMBINING CIE 127-2007 TOTAL FLUX MEASUREMENTS WITH THERMAL MEASUREMENTS OF LEDS WITH EXPOSED COOLING SURFACE This document is intended to be used in conjunction with the JESD51-50 series of standards, especially with JESD51-51 (Implementation of the Electrical Test Method for the Measurement of Real Thermal Resistance and Impedance of Light-emitting Diodes with Exposed Cooling Surface) document. This present document focuses on the measurement of the total radiant flux of LEDs in combination with the measurement of LEDs's thermal characteristics: guidelines on the implementation of the recommendations of the CIE 127-2007 document are provided. |
JESD51-52A | Nov 2022 | view |
TEMPERATURE, BIAS, AND OPERATING LIFE This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document. |
JESD22-A108G | Nov 2022 | view |
Wire Bond Pull Test Methods This test method provides a means for determining the strength and failure mode of a wire bonded to, and the corresponding interconnects on, a die or package bonding surface and may be performed on pre-encapsulation or post-encapsulation devices. |
JESD22-B120 | Nov 2022 | view |
Automotive Solid State Drive (SSD) Device Standard This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features for a solid state drive (SSD) targeted primarily at automotive applications. |
JESD312 | Nov 2022 | view |
Customer Notification for Environmental Compliance Declaration Deviations This standard is invoked when a supplier becomes aware that a product’s environmental compliance declaration they provided or made available to their customers had an error that might cause a customer to draw an incorrect conclusion about the compliance of the product to legal requirements. |
JESD262 | Nov 2022 | view |
OVERVIEW OF METHODOLOGIES FOR THE THERMAL MEASUREMENT OF SINGLE- AND MULTI-CHIP, SINGLE- AND MULTI-PN-JUNCTION LIGHT-EMITTING DIODES (LEDS) This document provides an overview of the methodology necessary for making meaningful thermal measurements on high-power light-emitting diodes (LEDs) built on single or multiple chips with one or more pn-junctions per chip. The actual methodology components are contained in separate detailed documents. |
JESD51-50A | Nov 2022 | view |
IMPLEMENTATION OF THE ELECTRICAL TEST METHOD FOR THE MEASUREMENT OF REAL THERMAL RESISTANCE AND IMPEDANCE OF LIGHT-EMITTING DIODES WITH EXPOSED COOLING SURFACE The purpose of this document is to specify, how LEDs thermal metrics and other thermally-related data are best identified by physical measurements using well established testing procedures defined for thermal testing of packaged semiconductor devices (published and maintained by JEDEC) and defined for characterization of light sources (published and maintained by CIE – the International Commission on Illumination). |
JESD51-51A | Nov 2022 | view |
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. |
JESD217A.01 | Nov 2022 | view |
Serial NOR Security Hardware Abstraction Layer This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device. |
JESD261 | Nov 2022 | view |
REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICES This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). |
JESD625C | Oct 2022 | view |
STANDARD - DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5 This standard defines the form, fit and function of DDR5 connectors for U/R/LR modules supporting channels with transfer rates up to 6.4 GT/S. It contains mechanical, electrical and reliability requirements for connector mated to a module with nominal thickness of 1.27 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the DDR5 connectors in client and server platforms. Item 11.14-213S |
PS-005B | Oct 2022 | view |
TERMS, DEFINITIONS AND UNITS GLOSSARY FOR LED THERMAL TESTING This document provides a unified collection of the commonly used terms and definitions in the area of LED thermal measurements. The terms and definitions provided herein extend beyond those used in the JESD51 family of documents, especially in JESD51-13, in order to include other often used terms and definitions in the area of light output measurements of LEDs. Definitions, symbols and notations regarding light output measurements used here are consistent with those defined in JESD77C.01 and with those defined by CIE (International Commission on Illumination), especially in the International Lighting Vocabulary, CIE S 017/E:2011 ILV and in the CIE 127-2007 document as well as in some other relevant standards of other standardization bodies from the solid-state lighting industry, e.g., ANSI/IESNA RP 16-05. |
JESD51-53A | Oct 2022 | view |
SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED) This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology. |
JEP164 | Oct 2022 | view |
STANDARD - DDR5 262 Pin SODIMM Connector Performance Standard This standard defines the form, fit and function of SODIMM DDR5 connectors for modules supporting channels with transfer rates 6.4 GT/S and beyond. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide performance standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR5 connectors in client and server platforms. Item 11.14-214S |
PS-006A | Oct 2022 | view |
PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03 This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5100 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5100 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 336.01C |
JESD301-2 | Oct 2022 | view |
Registration - Plastic Bottom Grid Array Ball, 0.80 mm X 0.65 mm Pitch Rectangular Family Package Designator: PBGA-B#[#]_I0p65... |
MO-311F | Oct 2022 | view |
TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES This test method is offered as a standardized procedure to determine the total dose limit of DRAMs by measuring its refresh time tRef degradation after the device is irradiated with an X-Ray dose. This test method is applicable to any packaged device that contains a DRAM die or any embedded DRAM structure. Some indirect test methods such as wafer level characterization of total dose induced changes in leakage of access transistors are not described in this standard but are permissible as long as a good correlation is established. |
JESD22-B130 | Sep 2022 | view |
Guideline for Evaluating dv/dt Robustness of SiC Power Devices, Version 1.0 This document provides stress procedures, general failure criteria and documentation guidelines such that the dv/dt robustness can be demonstrated, evaluated and documented. This document gives examples for test setups which can be used and the corresponding test conditions. Additionally, criteria are explained under which device manufacturers can select an appropriate test setup. |
JEP190 | Aug 2022 | view |
JEDEC MODULE SIDEBAND BUS (SidebandBus) This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.56A. |
JESD403-1B | Aug 2022 | view |
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 |
JESD8-20A.01 | Aug 2022 | view |
Registration - Silicon Bottom Grid Array Column, 0.048 mm x 0.055 mm Pitch Square Package Item: 11.4-996E Designator: SBGA-M7775[23828]_D0p073...
Item: 11.4-996 Access STP Files for MO-349A Cross Reference: DR4.26 |
MO-349A.01 | Aug 2022 | view |
Registration - Plastic Multi Connector 32 Pin, 1.00 MM Pitch 19.35 MM x 21.00 MM Socket Item 11.14-209A Designator: PMXC-G32[39]_1p0-R19p35x21p0Z3p2-N23p4T# |
SO-031A | Aug 2022 | view |
Registration - Plastic Bottom Grid Array Ball, 0.75 MM x 0.73 MM Pitch Rectangular Family Package Item 11-993 Designator: PBGA-B#[#]_I0p73... |
MO-353A | Aug 2022 | view |
Registration - Plastic Bottom Grid Array Ball, 0.65 MM Pitch Rectangular Family Package Designator: PBGA-B#[#]_I0p65... Item: 11.11-1024, Access STP Files for MO-246I Cross Reference: N/A
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MO-246I | Aug 2022 | view |
Registration - Plastic Multi Flange Mount Rectangular Family Item 11.10-460 Designator: PMFM K#_I... |
TO-247F | Aug 2022 | view |
Registration - Plastic Multi Small Outline, 1.14 MM pitch, 15.40 MM Body Width, Rectangular Family Package Item: 11.11-1023 Designator: PMSO-E#_I1p14-... |
MO-354A | Aug 2022 | view |
DDR5 SDRAM This standard defines the DDR5 SDRAM Specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Item 1848.99M. |
JESD79-5B | Aug 2022 | view |
Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension, Version 1.0 JESD231 was superseded by the renumbered JESD220-4 Version 1.01. |
JESD231 | Aug 2022 | view |
UNIVERSAL FLASH STORAGE, Version 4.0 This document replaces all past versions, however JESD220E, January 2020 (V 3.1), is available for reference only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. |
JESD220F | Aug 2022 | view |
Universal Flash Storage Host Controller Interface (UFSHCI), Version 4.0 This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY]. Item 206.25 |
JESD223E | Aug 2022 | view |
LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. |
JEP160A | Aug 2022 | view |
DDR5 SODIMM Raw Card Annex B. Version 1.0 This annex JESD309-S0-RCB, DDR5 Small Outline Dual Inline Memory Module with 0-bit ECC (EC0 SODIMM) Raw Card B Annex" defines the design detail of x8, 2 Package Ranks DDR5 NECC SODIMM. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard. |
JESD309-S0-RCB | Aug 2022 | view |
DDR5 UDIMM Raw Card Annex A This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card A Annex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A |
JESD308-U0-RCA | Jul 2022 | view |
DDR5 UDIMM Raw Card Annex A This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card A Annex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A |
JESD308-U0-RCA | Jul 2022 | view |
DDR5 UDIMM Raw Card Annex E This annex JESD308-U4-RCE, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) with 4-bit ECC (EC4 SODIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 ECC UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.12A |
JESD308-U4-RCE | Jul 2022 | view |
DDR5 UDIMM Raw Card Annex B This annex JESD308-U0-RCB, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card B Annex defines the design detail of x8, 2 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.11A |
JESD308-U0-RCB | Jul 2022 | view |
DDR5 UDIMM Raw Card Annex C This annex JESD308-U0-RCC, “DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.08A |
JESD308-U0-RCC | Jul 2022 | view |
Registration - Plastic Dual Small Outline, 1.00 MM pitch5.48 MM width Rectangular Family Package PDSO-G10_I1p)... Item 11.11-1005 |
MO-351A | Jun 2022 | view |
POD135 - 1.35 V PSEUDO OPEN DRAIN I/O Editorial, Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B |
JESD8-21C.01 | Jun 2022 | view |
POD125 - 1.25 V PSEUDO OPEN DRAIN I/O Editorial Terminology Update. This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices. |
JESD8-30A.01 | Jun 2022 | view |