Recently Published Documents

Title Document # Date Details
HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST)

The purpose of this test method is to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs severe conditions of temperature, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors which pass through it. This is a minor editorial edit to JESD22A110E, July 2015 approved by the formulating committee.

JESD22-A110E.01 May 2021 view
ACCELERATED MOISTURE RESISTANCE - UNBIASED HAST

The Unbiased HAST is performed for the purpose of evaluating the reliability of nonhermetic packaged solid-state devices in humid environments. It is a highly accelerated test which employs temperature and humidity under noncondensing conditions to accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. Bias is not applied in this test to ensure the failure mechanisms potentially overshadowed by bias can be uncovered (e.g., galvanic corrosion). This test is used to identify failure mechanisms internal to the package and is destructive.

JESD22-A118B.01 May 2021 view
PC-2700/PC-3200 Registered DIMM Design Specification Revision 2.2

Release 31. Item 2029.04This revision contains terminology updates only.

MODULE4.20.7 May 2021 view
REPLAY PROTECTED MONOTONIC COUNTER (RPMC) FOR SERIAL FLASH DEVICES

This document provides the requirements for an additional block called as Replay Protection Monotonic Counter. (RPMC) Replay Protection provides a building block towards providing additional security. This block requires modifications in both a Serial Flash device and Serial Flash Controller. The standard defines new commands for Replay Protected Monotonic Counter operations. A device that supports RPMC can support these new commands as defined in this standard.

JESD260 Apr 2021 view
SERIAL FLASH RESET SIGNALING PROTOCOL

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06.

JESD252.01 Apr 2021 view
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories

JEP166D Apr 2021 view
Registration - 84 Pin DDIMM, 0.60 mm Pitch Microelectronic Assembly

Designator: PDMA-N84-I0p6-R85p13xY#Z#R1p98x0p43 
Item: 11.14-191, Access STP Files for MO-335A

Cross Reference: N/A

MO-335A Apr 2021 view
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS

This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries.

JEP178 Apr 2021 view
Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).

Item 11.2-965(E)

DR-4.18A.01 Apr 2021 view
GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION

The scope of this document covers SiC-based PECS devices having a gate dielectric region biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are discussed as these are dominant for power device applications; however, the procedures apply to PMOS devices as well.

JEP184 Mar 2021 view
FLIP CHIP TENSILE PULL

The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test.

JESD22-B109C Mar 2021 view
Registration - 39 Pin Removable Memory, 1.00 mm Pitch Microelectronic Assembly

Designator: PBMA-N32[39]_Ip0-R14p1x18p1Z1p65-R0p71x1p1 
Item: 11.11-987, Access STP Files for MO-347A
Cross Reference: N/A

MO-347A Mar 2021 view
Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS

Item 142.01, 142.02.This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. 

MCP3.12.1 Mar 2021 view
NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION

RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01.

JEP300-1 Mar 2021 view
SYSTEM LEVEL ROWHAMMER MITIGATION

A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02.

JEP301-1 Mar 2021 view
HIGH BANDWIDTH MEMORY (HBM) DRAM

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L.

JESD235D Mar 2021 view
Addendum No. 1 to JESD79-4, 3D STACKED DRAM

This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G

JESD79-4-1B Feb 2021 view
ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)

This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A.

JESD209-4-1A Feb 2021 view
GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD

This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.  The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such  as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Item 1836.99E.

JESD250C Feb 2021 view

Pages