Recently Published Documents

Title Document # Date Details
PLASTIC FLANGE MOUNT, THROUGH-HOLE, 2.54 MM PITCH RECT PACKAGE (TRANSISTOR)

Package Designator:  PMDF-T5_I2p54...

Item # 11-1058

TO-282A Jun 2024 view
MCP and Discrete e•MMC, e•2MMC, and UFS

Item 142.12

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

 

MCP3.12.1-1 Jun 2024 view
DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH, MICROELECTRONIC ASSEMBLY

Designator:  XBNA-N#_I1p0_...

Item No:  14-229

MO-358B Jun 2024 view
Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1

This document provides guidelines for test methods and circuits to be used for measuring switching energy loss due to output capacitance hysteresis in semiconductor power devices.

JEP200 Jun 2024 view
JEDEC® Memory Module Label – for Compute Express Link® (CXL®)

This standard defines the labels that shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format.

JESD405-1B Jun 2024 view
Board Level Drop Test Method of Components for Handheld Electronic Products

This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components.

JESD22-B111A.01 Jun 2024 view
Information Requirements for the Qualification of Solid State Devices

This standard defines the requirements for the device qualification package, which the supplier provides to the customer.

JESD69D Jun 2024 view
Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA)

This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices.

JEP170A Jun 2024 view
Low Power Double Data Rate 4 (LPDDR4)

This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb.

JESD209-4E Jun 2024 view
DDR5 Registering Clock Driver Definition (DDR5RCD04)

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054.

JESD82-514.01 Jun 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, RECTANGULAR PACKAGE

Item 11-1051

Package Designator:  PDSO-G#_...

MO-203D May 2024 view
PLASTIC BOTTOM GRID, ARRAY BALL, 0.50 MM X 0.70 MM PITCH RECTANGULAR FAMILY PACKAGE

Item #11-1048A

Package Designator: PBGA-B#[#] I0p5...

MO-360A May 2024 view
PLASTIC QUAD FLATPACK, 28 TERMINAL PACKAGE

Item 11-1054

Package Designator: PQFP-N28_I4p0...

MO-339B May 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE)

Package Designator: P-PDSO-G2...

DO-215E May 2024 view
Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly

This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd  level terminal finish or material.

J-STD-609C.01 Apr 2024 view
SHIPPING AND HANDLING TRAY FOR LPDDR5 CAMM2 MODULE

Item #11.5-1057

CO-041A Apr 2024 view
PLASTIC DUAL SMALL OUTLINE, FLAT LEAD, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE) DO-219D Apr 2024 view
SHIPPING AND HANDLING TRAY FOR CAMM2 CONNECTOR

Designator: N/A

Item #: 11.5-1041

CO-040B Apr 2024 view
PMIC5020 Power Management IC Standard

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document.

The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

JESD301-4 Apr 2024 view
PLASTIC BOTTOM GRID, ARRAY BALL, 0.60 MM X 0.0675 MM PITCH RECTANGULAR FAMILY PACKAGE

Designator: PBGA--B264[294]_I0p60-R8p7X14p4Z1p0-C0p3Z#

Item: 11-1050 

JEP95 Registrations Main Page

MO-361A Apr 2024 view
Procedure for Reliability Characterization of Metal-Insulator-Metal Capacitors

This document defines the standards for achieving Reliability certification and qualification of on-chip MIM Capacitors and MIS Trench Capacitors.

JEP199 Apr 2024 view
Gate Dielectric Breakdown

This document describes procedures developed for estimating the overall integrity of gate dielectrics.

JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92.

JESD263 Mar 2024 view
JEDEC® Memory Module Reference Base Standard – for Compute Express Link® (CXL®)

This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL-attached memory modules.

JESD317A Mar 2024 view
Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices

This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM).

JESD625C.01 Mar 2024 view
Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress

This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages.

JEP154A Mar 2024 view
SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)

The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus.

JESD255 Mar 2024 view
DDR5 Clock Driver Definition (DDR5CKD01)

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5,
3= Clock Driver, 1= rev 01)

JESD82-531A.01 Feb 2024 view
Registration - Plastic Multi Small Outline, 17 Terminal, 1.20 mm Pitch Package. PMSO-E17.

Package Designator: PMSO-E17_I1p2...

Item 11.11-1046, 

MO-332B Jan 2024 view
SHIPPING AND HANDLING TRAY FOR DDR5 SODIMM MICROELECTRONIC ASSEMBLY

Designator: N/A

Item #: 11.5-995

 

CO-037A Jan 2024 view
Definition of “Low-Halogen” For Electronic Products

This standard provides terms and definitions for “low-halogen” electronic products.

JS709D Jan 2024 view
DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers.

JESD308A Jan 2024 view
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs). These DDR5 Clocked Unbuffered DIMMs (CUDIMMs) are intended for use as main memory when installed in Computers.

JESD323 Jan 2024 view
DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification

This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Clocked Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CSODIMMs). These DDR5 CSODIMMs are intended for use as main memory when installed in Computers, laptops and other systems.

JESD324 Jan 2024 view
Serial Interface for Data Converters

This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document.

JESD204D Dec 2023 view
PLASTIC DUAL SMALL OUTLINE, SURFACE TERMINAL, WETTABLE FLANK PACKAGE

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04

 

Item: 11-1044

Cross Reference: DR4.8, DR4.16, DR4.20

MO-340D Dec 2023 view
Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices

This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices.

JEP150A Dec 2023 view
XFM Device, Version 2.0

This standard specifies the mechanical and electrical characteristics of the XFM removable memory Device.

JESD233A Dec 2023 view
Power Cycling

This Test Method establishes a uniform method for performing solid state device package power cycling stress test.

JESD22-A122B Nov 2023 view
Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature

This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation.

JESD22-B112C Nov 2023 view
IC LATCH-UP TEST

This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress.

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880.

JESD78F.02 Nov 2023 view
Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications

This test method covers X-ray imaging for terrestrial applications on packaged devices.

JESD22-B121 Nov 2023 view
Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension

This standard specifies the extension specification of the UFS electrical interface and the memory device.

PLEASE NOTE: Revision and renumbering of JESD231 Version 1.0, August 2022

JESD220-4 Version 1.01 Nov 2023 view
Zoned Storage for UFS

The purpose of this standard is to describe Zoned Storage for UFS, which enables higher bandwidth, lower latency and to reduce write amplification.

JESD220-5 Nov 2023 view
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements

This publication establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format.

JEP181A Nov 2023 view
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema

In conjunction with JEP181A, for user support this file is the entire “XML Requirements Schema”.

JEP181_Schema_R2p0 Nov 2023 view
A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces

This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces.

JEP196 Nov 2023 view
Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices

This publication provides guidance to SiC product suppliers and related power electronic industries in their evaluation of bipolar degradation mechanism in SiC power devices.

JEP197 Nov 2023 view
Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices

This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches.

JEP198 Nov 2023 view
JEDEC Manual of Organization and Procedure

This Manual sets forth the mission and requirements of JEDEC as an independent incorporated Association governed by a Board of Directors.

 

JM21V Nov 2023 view
Design Requirements - BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM

BALL GRID ARRAY PACKAGE
BALL PITCH ≤ 0.80 MM
BODY SIZES ≤ 21 MM

Item 2-1038

DR-4.5O Nov 2023 view

Pages