Recently Published Documents

Title Document # Date Details
Registration - PLASTIC DUAL UPPER TO BOTTOM, 1.38 MM X1.00 MM PITCH CONNECTOR (CMT)

Designator: SO-032B_PDUtBXC-H644_I1p0-R17p15x78p0Z1p05
Item: 14-222
Cross Reference: N/A

SO-032B Nov 2023 view
Registration - 288 TERM DDR5 DIMM, 0.85 MM PITCH, MICROELECTRONIC ASSEMBLY

Designator: PDMA-N288-I0p85-R133p8x#p#7Z31p8R2p55x0p6

Item: 11.14-221, Access 

Cross Reference: MO-329, SO-023, GS-010

 

MO-329G Nov 2023 view
PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)

This standard facilitates the procurement and use of semiconductor die products provided in bare or bumped die form, and provides requirements and guidance to die suppliers as to the levels of as-delivered performance, quality and reliability expected. It also reflects the special needs of die product customers in terms of design and application data.

JESD49B.01 Oct 2023 view
JEDEC COMMITTEE SCOPE MANUAL

The JEDEC Board of Directors is responsible for establishing appropriate committees to conduct its standardization activities.  This publication identifies the service and product committees established by the Board of Directors and defines their scopes.

JM18U Oct 2023 view
DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS

This publication describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels.

JESD400-5B Oct 2023 view
DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH MICROELECTRONIC ASSEMBLY

Designator:  XBNA-N#_I1p0_...

Item No:  14-218

MO-358A Sep 2023 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2.00 MM PITCH, RECTANGULAR PACKAGE

Designator:  H-PDSO-G12_12p0-12p0x9p4Z2p8

Item No: 11-1034

 

 

MO-359A Sep 2023 view
DDR5 DIMM Labels

The following labels shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently.

JESD401-5B Aug 2023 view
Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This revision is to add R/C K1 for up to
PC4-3200 support for the DDR4 SO-DIMM R/C K Annex. Item 2228.68.

MODULE4.20.25.K.01 Aug 2023 view
Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch Rectangular Family

Designator: PBGA-B#[#]I0p5...

 

Item JC11.11-1036

Cross Reference: DR4.5

MO-276U Aug 2023 view
REGISTRATION - Upper PoP, Plastic Bottom Grid Array Ball, 0.40 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p40...
Item: 11.11-1035, Access 

Cross Reference: DR4.18

MO-344B Aug 2023 view
TS511X, TS521X Serial Bus Thermal Sensor Device Standard

This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document.

JESD302-1A Aug 2023 view
PLASTIC QUAD FLATPACK 1.27 MM PITCH, 5.00 MM X 6.00 MM RECTANGULAR FAMILY PACKAGE

Designator: PQFP-B#[#]_Ip27...

Item #: 11-1037 

MO-356A Aug 2023 view
Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package

Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1

 

Item: 11-1030

MO-341B Aug 2023 view
JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - COMPONENT LEVEL

This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data.

Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits

JS-001-2023 Jul 2023 view
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories

JEP166E Jul 2023 view
LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X

This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4).

JESD209-5C Jul 2023 view
Registration - Plastic Quad Flatpack, 0.65 mm Pitch, 3.30 mm Body, Square Family Package

Designator: PQFP-B#[#]_I0p65...

Item: 11-981E, Access STP Files for MO-346A

Cross Reference: N/A

MO-346A.01 Jun 2023 view
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1.

JS-002-2022 Jun 2023 view
GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTS

This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests.

JEP142 May 2023 view
Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification

This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing.

JEP114A May 2023 view
Statistical Process Control Systems

This standard specifies the general requirements of a statistical process control (SPC) system. 
This is a revision of JESD557C.

JESD557D May 2023 view
Graphics Double Data Rate (GDDR6) SGRAM Standard

This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212).

JESD250D May 2023 view
NAND Flash Interface Interoperability

This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations.

JESD230F.01 May 2023 view
HYBRIDS/MCM

This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence.

JESD93A May 2023 view
Guidelines for Supplier Performance Rating

This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria.

JEP146B May 2023 view
SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard.

JESD300-5B.01 May 2023 view
REGISTRATION - 288 PIN DDR5 DIMM SMT, 0.85 MM PITCH SOCKET OUTLINE

Designator: PDXC-LO288-I0p85-R162p0x6p5Z21p3-N5p20S3p1Z0p2

Item: 11.14-216, Access STP Files for SO-023C

Cross Reference: MO-329, GS-010C

 

SO-023D May 2023 view
DDR4 NVDIMM-N Design Standard

Terminology update.  

This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash.

JESD248A.01 Apr 2023 view
STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:

This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process.

JESD63 Apr 2023 view
STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALS

This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems.

JESD87 Apr 2023 view
Registration - Shipping and Handling Tray for M.2 Type 2230 Microelectronic Assembly

Designator: N/A
Item: 11.5-1004, Access STP File for CO-039A
Cross Reference: N/A

CO-039A Apr 2023 view
Registration - Shipping and Handling Tray for M.2 Type 2280 SSD Microelectronic Assembly

Designator: N/A
Item: 11.5-1001, Access STP File for CO-038A
Cross Reference: N/A

CO-038A Apr 2023 view
PMIC50x0 Power Management IC Standard

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as

used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

JESD301-1A.02 Rev. 1.8.5 Apr 2023 view
Temperature Cycling

This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing.

JESD22-A104F.01 Apr 2023 view
Registration - Plastic Quad Flat Package, Gull Wing and J-Lead, 0.65 MM Pitch

Designator: PQFP-E#_I0p65-R...
Item: 11.11-1028, Access STP File for MO-355A
Cross Reference: N/A

MO-355A Apr 2023 view
Graphics Double Data (GDDR4) SGRAM Standard

Item 1600.41, Terminology Update  

This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics Random

Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices.

SDRAM3.11.5.8 R16.01 Mar 2023 view
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications

Terminology update.  

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

JESD82-27.01 Mar 2023 view
RADIO FRONT END - BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE

Terminology update.  

This document establishes an interface standard for the data path and control plane interface functions for an RFIC component and/or a BBIC component.

JESD207.01 Mar 2023 view
Fully Buffered DIMM Design for Test, Design for Validation (DFx)

Terminology update.  

This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology.

JESD82-28A.01 Mar 2023 view
SILICON RECTIFIER DIODES:

Terminology update.   

This legacy document is a comprehensive users’ guide for silicon rectifier diode applications.

JESD282B.02 Mar 2023 view
RADIO FRONT END - BASEBAND (RF-BB) INTERFACE

Terminology update.  

This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC).

JESD96A.01 Mar 2023 view
COMPACT THERMAL MODEL OVERVIEW

Terminology update.

This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents.

JESD15-1.01 Mar 2023 view
DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS

Terminology update.   

Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications

JESD82-13A.01 Mar 2023 view
GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD

Terminology update.  

This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package

JESD232A.01 Mar 2023 view
Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package

Designator: PBGA-B#[#]_I0p...

 

Item: 11.11-988, Access STP Files for MO-210R

Cross Reference: DG4.5

https://www.jedec.org/filebrowser/download/1625

MO-210R Mar 2023 view
Registration - Plastic Bottom Grid Array Ball, 0.40 MM Pitch Rectangular Family Package

Designator: PBGA-B#[#}_I0p4...
Item: 11.11-1006E (Minor editorial Change), Access STP File for MO-352A.01
Cross Reference: N/A

MO-352A.01 Mar 2023 view
Part Model Thermal Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-T100A Mar 2023 view
Part Model SupplyChain Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-S100 Mar 2023 view
Part Model Assembly Process Classification Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts.  This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-A100A Mar 2023 view

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