Recently Published Documents

Ball Pitch = 0.40, 0.50, 0.65, 0.75 and 0.80 mm. Body sizes = ≤ 21 mm.Item 11.2-968E, Editorial Change.

Item 11-11.963 STP File for MO-336A

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06.

This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus  performance than legacy SPI memory implementations. Item 1775.15.

This document describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly.

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.10A

The purpose of this test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of environmental conditions experienced during the surface-mount soldering operation.

This specification defines the electrical and mechanical requirements for Raw Card D, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These DDR4 SO-DIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.41.

This annex describes the serial presence detect (SPD) values for all LPDDR modules covered in Document Release 2. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2254.02A

Item No. 11.2-951(S)

Item 11.11-952

This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. It will be shown through this document why realistic modifying of the ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different sections to give as many technical details as possible to support the purpose given in the abstract. In June 2009 the formulating committee approved the addition of the ESDA logo on the covers of this document. Please see Annex C for revision history.

Item 11.11-954

Item 11.11-953Outline Cross Reference: Design Registration 4.6 (DR4.6)