Recently Published Documents

Title Document # Date Details
Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card K, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.59A Editorial.

MODULE4.20.25.K.01 Apr 2019 view
Standard - Plastic Dual Small Outline (SO) Family, Gull Wing, 1.27 mm Pitch Package. PDSO-G.

Item 11.11-972(E).

MS-012G.01 Apr 2019 view
Registration - 262 Pin SODIMM, 0.50 mm Pitch Package

Item 14-192

MO-337A Apr 2019 view
Registration - 262 Pin DDR5 SODIMM, 0.50 mm Pitch Socket

Item 14-193

SO-024A Apr 2019 view
Annex C, R/C C, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card C, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.49.

MODULE4.20.28.C Mar 2019 view
LOW POWER DOUBLE DATA RATE 5 (LPDDR5)

This document has been replaced by JESD209-5A, however remains on the JEDEC Website for reference use only.

JESD209-5 Feb 2019 view
Design Requirements - Ball Grid Array Package (BGA)

Item 11.2-948E

DR-4.14J.01 Feb 2019 view
DYNAMIC ON-RESISTANCE TEST METHOD GUIDELINES FOR GaN HEMT BASED POWER CONVERSION DEVICES, VERSION 1.0

This document is intended for use in the GaN power semiconductor and related power electronic industries, and provides guidelines for measuring the dynamic ON-resistance of GaN power devices.

JEP173 Jan 2019 view
EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL STANDARD (5.1)

This document provides a comprehensive definition of the e•MMC Electrical Interface, its environment, and handling. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. The purpose of this standard is the definition of the e•MMC Electrical Interface, its environment and handling. It provides guidelines for systems designers. Item 67.14.

This document replaces all past versions, however links to the replaced versions are provided here for reference only: JESD84-B51, February 2015; JESD84-B50.1, July 2014 (Editorial revision of JESD84-B50); JESD84-B50, September 2013 (Revision of JESD84-B451); JESD84-B451, June 2012 (Revision of JESD84-B45, June 2011)

JESD84-B51A Jan 2019 view
SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES

The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability.

JEP143D Jan 2019 view
ANSI/ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1.

JS-002-2018 Jan 2019 view
Registration - Plastic Multi Position Flange Mount Mixed Technology, 0.10 in. Pitch Package

Item 11.10-457

TO-220L Jan 2019 view
GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING

These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors.  While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). 

JEP118A Dec 2018 view
DDR DIMM Product Label DIMM-LABEL4.19-1 Dec 2018 view
DDR2 DIMM Product Label

This section covers DDR2 DIMM labels.

DIMM-LABEL4.19.2 Dec 2018 view
DDR3 DIMM Product Label

This section covers DDR3 DIMM labels.

DIMM-LABEL4.19.3 Dec 2018 view
GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD

This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.  The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such  as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Item 1836.99D.

JESD250B Nov 2018 view
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

JESD22-A117E Nov 2018 view

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