Recently Published Documents

Title Document # Date Details
Design Requirements - Ball Grid Array Package (BGA)

Ball Pitch = 0.65, 0.75 and 0.80 mm, Body sizes >21mm. (For body sizes ≤ 21mm see Design Registration 4.5)

Item 11.2-969E. Editorial Change

DR-4.27F.01 Nov 2018 view
Design Requirements - Ball Grid Array Package (BGA) and Interstitial Ball Grid Array Package (IBGA)

Ball Pitch = 0.40, 0.50, 0.65, 0.75 and 0.80 mm. Body sizes = ≤ 21 mm.Item 11.2-968E, Editorial Change.

DR-4.5N.01 Nov 2018 view
Registration - Plastic Bottom Grid Array Ball, 0.80 mm Pitch Square Family Package

PBGA-B#(#)_I80...Item 11-961

MO-216F Nov 2018 view
Registration - Plastic Bottom Grid Array, Ball 0.70 mm Pitch, Square Family

Item 11-11.963 STP File for MO-336A

MO-336A Nov 2018 view
Labeling Requirements for DDR Series DIMMs

This standard provides the labels for the DDR Series DIMMs.

DIMM-LABEL4.19 Oct 2018 view
SERIAL FLASH RESET SIGNALING PROTOCOL

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06.

JESD252 Oct 2018 view
COMPONENT QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS (INCLUDING ADMINISTRATIVE QUALITY PROBLEMS)

This revision now encompasses administrative quality problems, in addition to the electrical and visual/mechanical quality problems that were addressed in the original release. A standard set of problem categories for each of these three types of component problems is presented for tracking and reporting purposes. A common set of customer and supplier expectations and requirements are set forth to help facilitate the successful problem analysis and corrective action of any type of component quality problem. Formerly known as EIA-671 (November 1996). Became JESD671-A after revision, December 1999.

JESD671D Oct 2018 view
Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE

This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus  performance than legacy SPI memory implementations. Item 1775.15.

JESD251-1 Oct 2018 view
MECHANICAL COMPRESSIVE STATIC STRESS TEST METHOD

This test method is intended for customers to determine the ability of a device to withstand the mechanical compressive static stress generated when a heat sink is being initially attached to the device, and to help the customer generate design rules for their heat sink design and validate their thermal solution. This test method does not assess the long-term effects of static stress.

JESD22-B119 Oct 2018 view
FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)

This document describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

JEP001-2A Sep 2018 view
FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites)

This document describes package-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

JEP001-3A Sep 2018 view
FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)

This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

JEP001-1A Sep 2018 view
Registration - Plastic Single Sided Hardware 7 Wire 1.2 mm Pitch Package. P-PSXH-W7_I120

Item No. 11.14-190

MO-334A Sep 2018 view
BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICs FOR HANDHELD ELECTRONIC PRODUCTS

The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly.

JESD22-B113B Aug 2018 view
POTENTIAL FAILURE MODE AND EFFECTS ANALYSIS (FMEA)

This publication applies to electronic components and subassemblies product and or process development, manufacturing processes and the associated performance requirements in customer applications. These areas should include, but are not limited to: package design, chip design, process development, assembly, fabrication, manufacturing, materials, quality, service, and suppliers, as well as the process requirements needed for the next assembly.

JEP131C Aug 2018 view
EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NON VOLATILE MEMORY DEVICES

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.10A

JESD251 Aug 2018 view
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

JESD47K Aug 2018 view
PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE

The purpose of this test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of environmental conditions experienced during the surface-mount soldering operation.

JESD22-B112B Aug 2018 view
PROCESS CHARACTERIZATION GUIDELINE

This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool.

JEP132A Aug 2018 view
Annex D, Raw Card D, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card D, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These DDR4 SO-DIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.41.

MODULE4.20.25.D Aug 2018 view
Annex F, R/C F, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card F, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.30.

MODULE4.20.26.F Aug 2018 view
Annex M, Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules, Document Release 2

This annex describes the serial presence detect (SPD) values for all LPDDR modules covered in Document Release 2. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2254.02A

SPD4.1.2.M-2 Aug 2018 view
Registration - Plastic Dual Small Outline, Flat, 2 Terminal Package. PDSO-F2.

Item 11.10-455.

DO-221B Aug 2018 view
Standard Practices and Procedures - Package Variation Designators

Item No. 11.2-951(S)

SPP-025C Aug 2018 view
Registration - Plastic Multi Small Outline, 17 Terminal, 1.20 mm Pitch Package. PMSO-E17.

Item 11.11-958 STP File for MO-332A

MO-332A Aug 2018 view
Registration - Plastic Bottom Flatpack 35 Terminal Package. PQFP-N35

Item 11.11-952

MO-333A Aug 2018 view
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories

JEP166C Jul 2018 view
RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION

This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. It will be shown through this document why realistic modifying of the ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different sections to give as many technical details as possible to support the purpose given in the abstract. In June 2009 the formulating committee approved the addition of the ESDA logo on the covers of this document. Please see Annex C for revision history.

JEP155B Jul 2018 view
Registration - Bottom Grid Array Ball, Square, 1.00 mm Pitch. PBGA-B.

Item 11.11-960

MO-331A Jun 2018 view
Registration - Ball Grid Array Family, Rectangular, 1.00 mm Pitch. PBGA.

Item 11.11-954

MO-234E Jun 2018 view
REGISTRATION - Ball Grid Array Family Rectangular, 0.60 mm x 0.70 mm Pitch. PBGA

Item 11.11-955

MO-330A Jun 2018 view
Registration - Fine Pitch Ball Grid Array Family, Rectangular, 0.80 mm Pitch. (V,T,L)FR-XBGA.

Item 11.11-953Outline Cross Reference: Design Registration 4.6 (DR4.6)

MO-210O Jun 2018 view
Registration - Fine Pitch Ball Grid Array Family, Rectangular , 0.50 mm Pitch. FR-XBGA, (L,T,V)FR-XBGA.

Item 11.11-956

MO-276N May 2018 view

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