Recently Published Documents

Title Document # Date Details
Registration - Plastic Multi Position Flange Mount Mixed Technology, 0.10 in. Pitch Package

Item 11.10-457

TO-220L Jan 2019 view
GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING

These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors.  While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). 

JEP118A Dec 2018 view
DDR DIMM Product Label DIMM-LABEL4.19-1 Dec 2018 view
DDR2 DIMM Product Label

This section covers DDR2 DIMM labels.

DIMM-LABEL4.19.2 Dec 2018 view
DDR3 DIMM Product Label

This section covers DDR3 DIMM labels.

DIMM-LABEL4.19.3 Dec 2018 view
GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD

This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.  The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such  as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Item 1836.99D.

JESD250B Nov 2018 view
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST

This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

JESD22-A117E Nov 2018 view
Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.29.

MODULE4.20.26.B Nov 2018 view
Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.37.

MODULE4.20.26.D Nov 2018 view
Annex A, R/C A, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card A, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.63.

MODULE4.20.25.A Nov 2018 view
Design Requirements - Ball Grid Array Package (BGA)

Ball Pitch = 0.65, 0.75 and 0.80 mm, Body sizes >21mm. (For body sizes ≤ 21mm see Design Registration 4.5)

Item 11.2-969E. Editorial Change

DR-4.27F.01 Nov 2018 view
Design Requirements - Ball Grid Array Package (BGA) and Interstitial Ball Grid Array Package (IBGA)

Ball Pitch = 0.40, 0.50, 0.65, 0.75 and 0.80 mm. Body sizes = ≤ 21 mm.Item 11.2-968E, Editorial Change.

DR-4.5N.01 Nov 2018 view
Registration - Plastic Bottom Grid Array, Ball 0.70 mm Pitch, Square Family

Item 11-11.963 STP File for MO-336A

MO-336A Nov 2018 view
Registration - Plastic Bottom Grid Array Ball, 0.80 mm Pitch Square Family Package

PBGA-B#(#)_I80...Item 11-961

MO-216F Nov 2018 view
Labeling Requirements for DDR Series DIMMs

This standard provides the labels for the DDR Series DIMMs.

DIMM-LABEL4.19 Oct 2018 view
SERIAL FLASH RESET SIGNALING PROTOCOL

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06.

JESD252 Oct 2018 view
Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE

This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus  performance than legacy SPI memory implementations. Item 1775.15.

JESD251-1 Oct 2018 view
MECHANICAL COMPRESSIVE STATIC STRESS TEST METHOD

This test method is intended for customers to determine the ability of a device to withstand the mechanical compressive static stress generated when a heat sink is being initially attached to the device, and to help the customer generate design rules for their heat sink design and validate their thermal solution. This test method does not assess the long-term effects of static stress.

JESD22-B119 Oct 2018 view
COMPONENT QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS (INCLUDING ADMINISTRATIVE QUALITY PROBLEMS)

This revision now encompasses administrative quality problems, in addition to the electrical and visual/mechanical quality problems that were addressed in the original release. A standard set of problem categories for each of these three types of component problems is presented for tracking and reporting purposes. A common set of customer and supplier expectations and requirements are set forth to help facilitate the successful problem analysis and corrective action of any type of component quality problem. Formerly known as EIA-671 (November 1996). Became JESD671-A after revision, December 1999.

JESD671D Oct 2018 view
FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)

This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

JEP001-1A Sep 2018 view
FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)

This document describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

JEP001-2A Sep 2018 view
FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites)

This document describes package-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

JEP001-3A Sep 2018 view
Registration - Plastic Single Sided Hardware 7 Wire 1.2 mm Pitch Package. P-PSXH-W7_I120

Item No. 11.14-190

MO-334A Sep 2018 view
BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICs FOR HANDHELD ELECTRONIC PRODUCTS

The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly.

JESD22-B113B Aug 2018 view

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