Recently Published Documents

Title Document # Date Details
Addendum No. 1 to JESD209-4 Low Power Double Data Rate 4X (LPDDR4X)

This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for a JEDEC compliant 16-bit per channel SDRAM device with either one or two channels

JESD209-4-1B May 2025 view
JESD271-4 HBM4 Bump Matrix Spreadsheet

The JESD271-4 HBM4 Bump Matrix Spreadsheet

JESD271-4 May 2025 view
PLASTIC BOTTOM GRID ARRAY, BALL, 0.35 MM PITCH, SQUARE FAMILY PACKAGE (UPPER POP)

Designator: PBGA-B#[#]_I0p35...

Item: 11-1078 

MO-367A May 2025 view
Solid-State Drive (SSD) Requirements and Endurance Test Method

This standard defines the conditions of use and the corresponding endurance and retention verification and qualification requirements for solid state drives.

JESD218C May 2025 view
288 TERM DDR5 DIMM, 0.85 MM PITCH, MICROELECTRONIC ASSEMBLY

Designator: PDMA-N288-I0p85-R136p8x5p57Z31p8R2p55x0p6

Item: 14-235 

Cross Reference: MO-329, SO-023, GS-010

 

MO-329J Apr 2025 view
High Bandwidth Memory (HBM4) DRAM

The HBM4 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM4 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR).

Click here for the JESD271-4 HBM4 Bump Matrix Spreadsheet.

JESD270-4 Apr 2025 view
SILICON BOTTOM GRID ARRAY COLUMN, 0.035 MM X 0.055 MM PITCH RECTANGULAR PACKAGE (HBM4)

Designator: SBGA-M8236[56028]_I0p65-R14p175x10p975Z0p81

Item #: 4-1079

 

MO-362B Apr 2025 view
High Bandwidth Memory (HBM3) DRAM

The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR).

JESD238B.01 Apr 2025 view
PMIC5020 Power Management IC Standard

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document.

 

The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

JESD301-4A Mar 2025 view
DICTIONARY OF TERMS FOR SOLID-STATE TECHNOLOGY, 8th Edition

This reference for technical writers and educators, manufacturers, and buyers and users of discrete solid state devices is now available. It should aid the technical committees of JEDEC in the avoidance of multiple definitions and reduce the proliferation of redundant definitions. The long-term goal is to include definitions from all JEDEC publications and standards. Each of the approximately two thousand entries is referenced to its source publication, and an annex listing the names of the source publications and their releases dates is included. All entries were reviewed for punctuation, grammar, and clarity, as well as accuracy, and reworded if such was considered warranted. The purpose of this dictionary is to promote the uniform use of terms, definitions, abbreviations, and symbols throughout the solid state industry

JESD88G Mar 2025 view
JEDEC Manual of Organization and Procedure

This Manual sets forth the mission and requirements of JEDEC as an independent incorporated Association governed by a Board of Directors.

JM21W Mar 2025 view
DDR5 Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 SODIMM) Raw Card D Annex

This annex, JESD309-S4-RCD, DDR5 Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 SODIMM) Raw Card D Annex, defines the design detail of x8, 1 Package Rank DDR5 SODIMM with 4-bit ECC. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard.

JESD309-S4-RCE Mar 2025 view
DDR5 Small Outline Dual Inline Memory Module (SODIMM) Raw Card C Annex

This annex, JESD309-S0-RCC, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Raw Card C Annex, defines the design detail of x16, 1 Package Ranks DDR5 SODIMM. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard.

JESD309-S0-RCC Mar 2025 view
DDR5 Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 SODIMM) Raw Card D Annex

This annex, JESD309-S4-RCD, DDR5 Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 SODIMM) Raw Card D Annex, defines the design detail of x8, 1 Package Rank DDR5 SODIMM with 4-bit ECC. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard.

JESD309-S4-RCD Mar 2025 view
DDR5 Small Outline Dual Inline Memory Module (SODIMM) Raw Card B Annex

This annex, JESD309-S0-RCB, DDR5 Small Outline Dual Inline Memory Module with 0-bit ECC (EC0 SODIMM) Raw Card B Annex", defines the design detail of x8, 2 Package Ranks DDR5 NECC SODIMM. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard.

JESD309-S0-RCB Mar 2025 view
DDR5 Small Outline Dual Inline Memory Module (SODIMM) Raw Card A Annex

This annex, JESD309-S0-RCA, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Raw Card A Annex, defines the design detail of x8, 1 Package Rank DDR5 SODIMM. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard.

JESD309-S0-RCA Mar 2025 view
DDR5 Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 UDIMM) Raw Card E Annex

This annex JESD308-U4-RCE, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) with 4-bit ECC (EC4 SODIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 ECC UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard.

JESD308-U4-RCE Mar 2025 view
DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card A Annex

This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card A Annex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard.

JESD308-U0-RCA Mar 2025 view
DDR5 Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 UDIMM) Raw Card D Annex

This annex JESD308-U4-RCD, DDR5 Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4UDIMM) Raw Card D Annex defines the design detail of x8, 1 Package Rank DDR5 UDIMM with 4-bit ECC. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard.

JESD308-U4-RCD Mar 2025 view
DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card C Annex

This annex JESD308-U0-RCC, “DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.08A

JESD308-U0-RCC Mar 2025 view
DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card B Annex

This annex, JESD308-U0-RCB, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card B Annex, defines the design detail of x8, 2 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard.

JESD308-U0-RCB Mar 2025 view
DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card D Annex

This standard, JESD305-R8-RCD, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card D Annex, defines the design detail of x8, 1 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard.

JESD305-R8-RCD Feb 2025 view
DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card C Annex

This standard, JESD305-R8-RCC, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card C Annex, defines the design detail of x4, 1 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard.

JESD305-R8-RCC Feb 2025 view
DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard

This standard defines the electrical and mechanical requirements for 288-position, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These Registered DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments.

JESD305A Feb 2025 view
DDR5 Clocked Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4 CUDIMM) Raw Card E Annex

This annex, JESD323-B4-RCE, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 CUDIMM. The common feature of DDR5 CUDIMM such as the connector pinout can be found in the JESD323, DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Standard.

JESD323-B4-RCE Feb 2025 view
DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card A Annex

This annex, JESD305-R8-RCA, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card A Annex, defines the design detail of x4, 2 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard.

JESD305-R8-RCA Feb 2025 view
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Standard

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs). These DDR5 Clocked Unbuffered DIMMs (CUDIMMs) are intended for use as main memory when installed in Computers.

JESD323A Feb 2025 view
DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Standard

This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Clocked Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CSODIMMs). These DDR5 CSODIMMs are intended for use as main memory when installed in Computers, laptops and other systems.

JESD324A Feb 2025 view
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card B Annex

This annex, JESD323-A0-RCB, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card B Annex", defines the design detail of x8, 2 Package Ranks DDR5 CUDIMM. The common feature of DDR5 CUDIMM such as the connector pinout can be found in the JESD323, DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Standard.

JESD323-A0-RCB Feb 2025 view
DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers.

JESD308B Feb 2025 view
DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard

This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM SODIMMs). These DDR5 SODIMMs are intended for use as main memory when installed in Computers, laptops and other systems.

JESD309A Feb 2025 view
DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card B Annex

This annex JESD324-V0-RCB, “DDR5 Clocked Small Outline Dual Inline Memory Module with 0-bit ECC (EC0 CSODIMM) Raw Card B Annex" defines the design detail of x8, 2 Package Ranks DDR5 NECC Clocked SODIMM. The common feature of DDR5 CSODIMM such as the connector pinout can be found in the JESD324, DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Standard.

JESD324-V0-RCB Feb 2025 view
Graphics Double Data Rate 7 SGRAM Standard (GDDR7)

This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.

 

JESD239B Feb 2025 view
PMIC5120 Power Management IC Standard

This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5120 refers to the device specified by this document.

The purpose is to provide a standard for the PMIC5120 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Unless otherwise noted in the document, any illegal operation is not allowed and device operation is not guaranteed.

JESD301-6 Feb 2025 view
SHIPPING AND HANDLING TRAY FOR DDR5 2U DIMM

Designator: N/A

Item #: 5-1074

CO-042A Feb 2025 view
STANDARD MANUFACTURER'S IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

JEP106BL Feb 2025 view
DESIGN GUIDE 4.10, GENERIC SHIPPING & HANDLING MATRIX TRAY

Item 102-1029S

DG-4.10E Feb 2025 view
288 TERMINAL POSITIONS (287 TERMINALS) DDR5 DIMM SMT 0.85MM PITCH SOCKET

Designator: PDXC-LO288-I0p85-R162p0x6p5Z21p3-N5p20S3p1Z0p2

Item: 11.14-233, Access STP Files for SO-023C

Cross Reference: MO-329, GS-010C

 

SO-023E Feb 2025 view
PART MODEL SCHEMAS

This download includes all files under the parent schema JEP30-10v8-0-0 (Committees: JC-11, JC-11.2) including:

  • JEP30-A101v2-0-4 (Assembly Process),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-E101v5-0-0 (Electrical),
    • Committees: JC-11, JC-11.2, JC-16
  • JEP30-P101v8-0-0 (Package),
    • Committees: JC-11, JC-11.2
  • JEP30-S101v1-1-1 (Supply Chain),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-T101v2-0-4 (Thermal)
    • Committees: JC-11, JC-11.2, JC-15
  • JEP30-K101v1-0-0 (Design Rule Kits)
     
  • JEP30-M101v1-0-0 (ECAD Models Guidelines)
     
  • JEP30-D10v5-0-0 (Types Dictionary)
    • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

JEP30-10v8-0-0 Feb 2025 view
Part Model Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure.

For more information visit the main JEP30 webpage.

JEP30F Feb 2025 view
Part Model Package Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-P100G Feb 2025 view
Part Model Thermal Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-T100B.01 Feb 2025 view
PartModel Generated ECAD - Models Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the “generated ECAD model” subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-M100 Feb 2025 view
Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-E100G Feb 2025 view
PartModel Design Rule Kits Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the “Design Kit” subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-K100 Feb 2025 view
Part Model Assembly Process Classification Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts.  This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-A100B.01 Feb 2025 view
Descriptive Designation System for Electronic-device Packages and Footprints

This standard establishes requirements for the generation of electronic-device package designators for JEDEC.

JESD30O Feb 2025 view
Part Model Supply Chain Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-S100A.02 Feb 2025 view
PLASTIC DUAL SMALL OUTLINE GULL WING, 1.27 MM PITCH PACKAGE

Designator: PDSO-G#_I127-##...

Item 11-1061

MS-012H Feb 2025 view
PLASTIC BOTTOM GRID ARRAY, BALL, 0.35 MM PITCH, RECTANGULAR FAMILY PACKAGE (UPPER POP)

Designator: PBGA-B#[#]_I0p35...

Item: 11-1075

 

 

MO-366A Feb 2025 view

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