Recently Published Documents

Title Document # Date Details
INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES

Terminology update.This device is a one-chip spectrum analyzer that operates in the frequency range from 1 to 2 GHz.It requires no external components except some filtering of the voltage supply (one inductor, one bypass capacitor).The frequency of the VCO is adjusted by an internal DAC. No PLL loop is used to lock the VCO to a reference frequency. A counter is used to determine the VCO frequency.

JESD82-22.01 Feb 2023 view
DEFINITION OF THE SSTU32864 1.8 V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS:

Terminology update.This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications.

JESD82-7A.01 Feb 2023 view
DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

 Terminology update.This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar high density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410 MHz.

JESD82-24.01 Jan 2023 view
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

Terminology update.This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications.The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

JESD82-29A.01 Jan 2023 view
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS:

Terminology update.This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the 32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications.

JESD82-6A.01 Jan 2023 view
DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS:

Terminology update.This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTVN16857 14-bit SSTL_2 registered buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM applications.

JESD82-3B.01 Jan 2023 view
LRDIMM DDR3 MEMORY BUFFER (MB)

Terminology update.

The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components.

JESD82-30.01 Jan 2023 view
DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)

Terminology update.

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications.

JESD82-31A.01 Jan 2023 view
DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

Terminology update.This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications.

JESD82-25.01 Jan 2023 view
DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

Terminology update.  This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUB32868 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

JESD82-26.01 Jan 2023 view
DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

Terminology update.  This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S869 and SSTUA32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. The SSTUA32S869 and SSTUA32D869 are identical in functionality to the SSTU32S869 and SSTU32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz.

JESD82-23.01 Jan 2023 view
GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD

Terminology update. This document defines the Graphics Double Data Rate 5 (GDDR5) Synchronous Graphics Random Access Memory (SGRAM), including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC standard compatible 512 Mb through 8 Gb x32 GDDR5 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR5 SGRAM vendors providing JEDEC standard compatible devices. Some aspects of the GDDR5 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. Item 1733.70B

JESD212C.01 Jan 2023 view
Joint ESDA/JEDEC - CDM Technical User Guide

This report only covers the procedures and requirements specified in ANSI/ESDA/JEDEC JS-002.

JTR002-01-22 Jan 2023 view
DDR5 Serial Presence Detect (SPD) Contents

This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be used by the system's BIOS in order to properly initialize and optimize the system memory channels.

JESD400-5A.01 Jan 2023 view
FBDIMM: ADVANCED MEMORY BUFFER (AMB)

This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided.

JESDJESD82-20A.01 Jan 2023 view
HIGH BANDWIDTH MEMORY (HBM3) DRAM

The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR).

JESD238A Jan 2023 view
Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs

This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis.

JEP183A Jan 2023 view
SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS

This publication is a guideline to assist manufacturers of integrated circuits in defining conditions for burn-in and life test of their products to meet quality and reliability performance requirements of MIL-PRF-38535.

JEP163A Jan 2023 view
Guidelines for Gate Charge (QG) Test Method for SiC MOSFET

This publication defines a QGS, TOT, QGD and QGS, TH which can be extracted from a measured QG waveform for SiC MOSFETs.

JEP192 Jan 2023 view
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1.

JS-002-2022 Jan 2023 view
Survey On Latch-Up Testing Practices and Recommendations for Improvements

This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry.

JEP193 Jan 2023 view
THERMAL SHOCK

This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes.

JESD22-A106B.02 Jan 2023 view
JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)

The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations.

J-STD-020F Dec 2022 view
PROCESS CHARACTERIZATION GUIDELINE

This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool.

JEP132A.01 Dec 2022 view
JEDEC Manual of Organization and Procedure

The mission of JEDEC is to serve the solid state industry by creating, publishing, and promoting global acceptance of standards, and by providing a forum for technical exchange on leading industry topics. This manual provides guidance for JEDEC members and staff to perform their functions correctly in the standardization process.
NOTE   The .pdf file has been updated as of  1/12/2023, there was an side comment in 7.2 that was included at time of conversion and has been removed.

JM21U Dec 2022 view
JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices

This method provides users with an acoustic microscopy process flow for detecting anomalies (delaminations, cracks, mold compound voids, etc.) nondestructively in encapsulated electronic devices while achieving reproducibility.

J-STD-035A Dec 2022 view
IC LATCH-UP TEST

This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880.

JESD78F.01 Dec 2022 view
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

JESD47L Dec 2022 view
Secure Serial Flash Bus Transactions

This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure.

JESD254 Dec 2022 view
GUIDELINES FOR COMBINING CIE 127-2007 TOTAL FLUX MEASUREMENTS WITH THERMAL MEASUREMENTS OF LEDS WITH EXPOSED COOLING SURFACE

This document is intended to be used in conjunction with the JESD51-50 series of standards, especially with JESD51-51 (Implementation of the Electrical Test Method for the Measurement of Real Thermal Resistance and Impedance of Light-emitting Diodes with Exposed Cooling Surface) document. This present document focuses on the measurement of the total radiant flux of LEDs in combination with the measurement of LEDs's thermal characteristics: guidelines on the implementation of the recommendations of the CIE 127-2007 document are provided.

JESD51-52A Nov 2022 view
TEMPERATURE, BIAS, AND OPERATING LIFE

This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document.

JESD22-A108G Nov 2022 view
Wire Bond Pull Test Methods

This test method provides a means for determining the strength and failure mode of a wire bonded to, and the corresponding interconnects on, a die or package bonding surface and may be performed on pre-encapsulation or post-encapsulation devices. 

JESD22-B120 Nov 2022 view
Automotive Solid State Drive (SSD) Device Standard

This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features for a solid state drive (SSD) targeted primarily at automotive applications.

JESD312 Nov 2022 view
IMPLEMENTATION OF THE ELECTRICAL TEST METHOD FOR THE MEASUREMENT OF REAL THERMAL RESISTANCE AND IMPEDANCE OF LIGHT-EMITTING DIODES WITH EXPOSED COOLING SURFACE

The purpose of this document is to specify, how LEDs thermal metrics and other thermally-related data are best identified by physical measurements using well established testing procedures defined for thermal testing of packaged semiconductor devices (published and maintained by JEDEC) and defined for characterization of light sources (published and maintained by CIE – the International Commission on Illumination).

JESD51-51A Nov 2022 view
OVERVIEW OF METHODOLOGIES FOR THE THERMAL MEASUREMENT OF SINGLE- AND MULTI-CHIP, SINGLE- AND MULTI-PN-JUNCTION LIGHT-EMITTING DIODES (LEDS)

This document provides an overview of the methodology necessary for making meaningful thermal measurements on high-power light-emitting diodes (LEDs) built on single or multiple chips with one or more pn-junctions per chip. The actual methodology components are contained in separate detailed documents.

JESD51-50A Nov 2022 view
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures.

JESD217A.01 Nov 2022 view
DESCRIPTIVE DESIGNATION SYSTEM FOR ELECTRONIC-DEVICE PACKAGES

This standard establishes requirements for the generation of electronic-device package designators for the JEDEC Solid State Technology Association. The requirements herein are intended to ensure that such designators are presented in as uniform a manner as practicable. Item 11.2-1002.
NOTE IF YOU DOWNLOADED THIS DOCUMENT PRIOR TO 12/16/2022 PLEASE DISCARD AND VIEW AGAIN, PREVIOUS VERSION CONTAINED FORMAT ISSUES.

JESD30J Nov 2022 view
Customer Notification for Environmental Compliance Declaration Deviations

This standard is invoked when a supplier becomes aware that a product’s environmental compliance declaration they provided or made available to their customers had an error that might cause a customer to draw an incorrect conclusion about the compliance of the product to legal requirements.

JESD262 Nov 2022 view
Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS

Item 140.07B.
This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. 

MCP3.12.1 Nov 2022 view
Serial NOR Security Hardware Abstraction Layer

This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device.

JESD261 Nov 2022 view
Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch Rectangular Family

Designator: PBGA-B#[#]I0p5...Item 11-1025Cross Reference: DR4.5

MO-276S Nov 2022 view
STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm

JEP106BF Oct 2022 view
REQUIREMENTS FOR HANDLING ELECTROSTATIC-DISCHARGE-SENSITIVE (ESDS) DEVICES

This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM).

JESD625C Oct 2022 view
STANDARD - DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5

This standard defines the form, fit and function of DDR5 connectors for U/R/LR modules supporting channels with transfer rates up to 6.4 GT/S. It contains mechanical, electrical and reliability requirements for connector mated to a module with nominal thickness of 1.27 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the DDR5 connectors in client and server platforms. Item 11.14-213S

PS-005B Oct 2022 view
TERMS, DEFINITIONS AND UNITS GLOSSARY FOR LED THERMAL TESTING

This document provides a unified collection of the commonly used terms and definitions in the area of LED thermal measurements. The terms and definitions provided herein extend beyond those used in the JESD51 family of documents, especially in JESD51-13, in order to include other often used terms and definitions in the area of light output measurements of LEDs. Definitions, symbols and notations regarding light output measurements used here are consistent with those defined in JESD77C.01 and with those defined by CIE (International Commission on Illumination), especially in the International Lighting Vocabulary, CIE S 017/E:2011 ILV and in the CIE 127-2007 document as well as in some other relevant standards of other standardization bodies from the solid-state lighting industry, e.g., ANSI/IESNA RP 16-05.

JESD51-53A Oct 2022 view
SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)

This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology.

JEP164 Oct 2022 view
STANDARD - DDR5 262 Pin SODIMM Connector Performance Standard

This standard defines the form, fit and function of SODIMM DDR5 connectors for modules supporting channels with transfer rates 6.4 GT/S and beyond. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide performance standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR5 connectors in client and server platforms. Item 11.14-214S

PS-006A Oct 2022 view
PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03

This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5100 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5100 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 336.01C

JESD301-2 Oct 2022 view
PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1.83

Definition of PMIC5000, PMIC5010 Voltage Regulator Device for Memory Module Applications. Item 325.29D. Minor Editorial Revision, see Annex.

JESD301-1A.01 Oct 2022 view
Registration - Plastic Bottom Grid Array Ball, 0.80 mm X 0.65 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p65...
Item: 11.11-1026, Access STP File for MO-311E
Cross Reference: DR4.5

MO-311F Oct 2022 view

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