Recently Published Documents

This publication provides guidelines for representation of threshold voltage and transfer characteristic of SiC MOS device in datasheets.

This document replaces all prior versions; however, JESD220F August 2022 (version 4.0) remains available for reference purposes.

This standard defines a UFS Universal Flash Storage electrical interface and a UFS memory device.

This standard, “JESD323-A0-RCC, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 Clocked UDIMM.

Designator: SO-032D_PDUtBXC-H736_I1p0-R17p15x78p0Z1p05
Item: 14-231
Cross Reference: N/A

This standard defines the labels that shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently.

This standard defines the electrical and mechanical requirements for Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LP5 SDRAM CAMM2s).

This standard, JESD324-V0-RCA, “DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Ranks DDR5 CSODIMM with Clock Driver.

This standard, JESD323-A0-RCA, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Rank DDR5 NECC CUDIMM with Clock Driver.

This standard, JESD324-W4-RCD, “DDR5 Clocked Small Outline Dual Inline Memory Module with 4-bit ECC (EC4 CSODIMM) Raw Card D Annex” defines the design detail of x8, 1 Package Ranks DDR5 CSODIMM with Clock Driver.

This download includes all files under the parent schema JEP30-10v7-0-0 (Committees: JC-11, JC-11.2) including:

• JEP30-A101v2-0-3 (Assembly Process),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-E101v4-1-0 (Electrical),
  
  • Committees: JC-11, JC-11.2, JC-16
• JEP30-P101v7-0-0 (Package),
  
  • Committees: JC-11, JC-11.2
• JEP30-S101v1-1-0 (Supply Chain),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-T101v2-0-3 (Thermal)
  
  • Committees: JC-11, JC-11.2, JC-15
• JEP30-D10v4-0-0 (Types Dictionary)
  
  • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model.

For more information visit the main JEP30 webpage.

This standard, JESD324-V0-RCC, "DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) RawCard C Annex" defines the design detail of x16, 1 Package Ranks DDR5 CSODIMM with Clock Driver.

This standard defines the Low Power Double Data Rate interface for Non-Volatile Memory (LPDDR4XNVM) Standard. This standard describes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements

for a JEDEC compliant 16 bit single channel LPDDR4X-NVM device. LPDDR4X-NVM density ranges from 128Mb through 32Gb.

This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data.

Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits

This standard defines the form, fit and function of SODIMM DDR5 connectors for modules supporting channels with transfer rates 6.4 GT/S and beyond. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide performance standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR5 connectors in client and server platforms. Item 14-226

This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.

Item #: 11-1067

Package Designator: PDSO-G3(6)-i0p95....

This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later.

This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels.

The publication provides methodologies for measurements to qualify a new semiconductor wafer process.

Item: 11-1065

Designator: PMSO-E#_I1p14-...

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure.

For more information visit the main JEP30 webpage.

Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser.  Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32

Designator:PDFN-N[#]_I1p27...

Item #: 11-1063