Recently Published Documents

Title Document # Date Details
MCP and Discrete e•MMC, e•2MMC, and UFS

Item 142.12.

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

 

MCP3.12.1-1 Jun 2024 view
LPDDR5/5X Serial Presence Detect (SPD) Contents

This publication describes the serial presence detect (SPD) values for all LPDDR5/5X memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non-volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding.

JESD406-5 Jun 2024 view
LPDDR5/5X Serial Presence Detect (SPD) Contents

This publication describes the serial presence detect (SPD) values for all LPDDR5/5X memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non-volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding.

JESD406-5 Jun 2024 view
PLASTIC DUAL UPPER TO BOTTOM, 1.38 MM X1.00 MM PITCH CONNECTOR (CMT)

Designator: SO-032B_PDUtBXC-H644_I1p0-R17p15x78p0Z1p05
Item: 14-227
Cross Reference: N/A

SO-032C Jun 2024 view
LPDDR5 CAMM2, 1.38 MM X 1.00 MM PITCH MICROELECTRONIC ASSEMBLY

Designator: XBMA-H644_I1p0_R78p0x23p0Z2p6

Item #:  14-228

MO-357C Jun 2024 view
DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH, MICROELECTRONIC ASSEMBLY

Designator:  XBNA-N#_I1p0_...

Item No:  14-229

MO-358B Jun 2024 view
Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1

This document provides guidelines for test methods and circuits to be used for measuring switching energy loss due to output capacitance hysteresis in semiconductor power devices.

JEP200 Jun 2024 view
JEDEC® Memory Module Label – for Compute Express Link® (CXL®)

This standard defines the labels that shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format.

JESD405-1B Jun 2024 view
288 TERM DDR5 DIMM, 0.85 MM PITCH, MICROELECTRONIC ASSEMBLY

Designator: PDMA-N288-I0p85-R133p8x#p#7Z31p8R2p55x0p6

Item: 11.14-224, Access 

Cross Reference: MO-329, SO-023, GS-010

 

MO-329H.01 Jun 2024 view
Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA)

This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices.

JEP170A Jun 2024 view
Board Level Drop Test Method of Components for Handheld Electronic Products

This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components.

JESD22-B111A.01 Jun 2024 view
Information Requirements for the Qualification of Solid State Devices

This standard defines the requirements for the device qualification package, which the supplier provides to the customer.

JESD69D Jun 2024 view
DDR5 Registering Clock Driver Definition (DDR5RCD04)

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054.

JESD82-514.01 Jun 2024 view
Low Power Double Data Rate 4 (LPDDR4)

This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb.

JESD209-4E Jun 2024 view
DDR5 DIMM Labels

This standard defines the labels that shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently.

JESD401-5B.01 May 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, RECTANGULAR PACKAGE

Item 11-1051

Package Designator:  PDSO-G#_...

MO-203D May 2024 view
PLASTIC BOTTOM GRID, ARRAY BALL, 0.50 MM X 0.70 MM PITCH RECTANGULAR FAMILY PACKAGE

Item #11-1048A

Package Designator: PBGA-B#[#] I0p5...

MO-360A May 2024 view
PLASTIC QUAD FLATPACK, 28 TERMINAL PACKAGE

Item 11-1054

Package Designator: PQFP-N28_I4p0...

MO-339B May 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE)

Package Designator: P-PDSO-G2...

DO-215-E May 2024 view
PART MODEL SCHEMAS

This download includes all files under the parent schema JEP30-10v5-0-1 (Committees: JC-11, JC-11.2) including:

  • JEP30-A101v2-0-2 (Assembly Process),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-E101v3-0-2 (Electrical),
    • Committees: JC-11, JC-11.2, JC-16
  • JEP30-P101v5-0-0 (Package),
    • Committees: JC-11, JC-11.2
  • JEP30-S101v1-0-2 (Supply Chain),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-T101v2-0-2 (Thermal)
    • Committees: JC-11, JC-11.2, JC-15
  • JEP30-D10v3-0-1 (Types Dictionary)
    • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

JEP30-10v5-0-1 May 2024 view
STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

JEP106BJ May 2024 view
Graphics Double Data Rate 7 SGRAM Standard (GDDR7)

This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.  

ATTENTION USERS: Be advised that the formulating subcommittee is working on an update that may require host design changes. Members of the subcommittee may contact the TG for more information.

JESD239.01 Apr 2024 view
SHIPPING AND HANDLING TRAY FOR LPDDR5 CAMM2 MODULE

Item #11.5-1057

CO-041A Apr 2024 view
Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly

This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd  level terminal finish or material.

J-STD-609C.01 Apr 2024 view
DDR5 SDRAM

Version 1.30

This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4).

JESD79-5C Apr 2024 view
SHIPPING AND HANDLING TRAY FOR CAMM2 CONNECTOR

Designator: N/A

Item #: 11.5-1041

CO-040B Apr 2024 view
PLASTIC DUAL SMALL OUTLINE, FLAT LEAD, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE) DO-219D Apr 2024 view
PMIC5020 Power Management IC Standard

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document.

The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

JESD301-4 Apr 2024 view
PLASTIC BOTTOM GRID, ARRAY BALL, 0.60 MM X 0.0675 MM PITCH RECTANGULAR FAMILY PACKAGE

Designator: PBGA--B264[294]_I0p60-R8p7X14p4Z1p0-C0p3Z#

Item: 11-1050 

JEP95 Registrations Main Page

MO-361A Apr 2024 view
Procedure for Reliability Characterization of Metal-Insulator-Metal Capacitors

This document defines the standards for achieving Reliability certification and qualification of on-chip MIM Capacitors and MIS Trench Capacitors.

JEP199 Apr 2024 view
Gate Dielectric Breakdown

This document describes procedures developed for estimating the overall integrity of gate dielectrics.

JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, and JESD35-2.

JESD263 Mar 2024 view
JEDEC® Memory Module Reference Base Standard – for Compute Express Link® (CXL®)

This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL-attached memory modules.

JESD317A Mar 2024 view
Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress

This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages.

JEP154A Mar 2024 view
Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices

This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM).

JESD625C.01 Mar 2024 view
SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)

The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus.

JESD255 Mar 2024 view
Part Model Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure.

For more information visit the main JEP30 webpage.

JEP30D Feb 2024 view
Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-E100D Feb 2024 view
Part Model Package Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-P100D Feb 2024 view
DDR5 Clock Driver Definition (DDR5CKD01)

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5,
3= Clock Driver, 1= rev 01)

JESD82-531A.01 Feb 2024 view
Registration - Plastic Multi Small Outline, 17 Terminal, 1.20 mm Pitch Package. PMSO-E17.

Package Designator: PMSO-E17_I1p2...

Item 11.11-1046, 

MO-332B Jan 2024 view
SHIPPING AND HANDLING TRAY FOR DDR5 SODIMM MICROELECTRONIC ASSEMBLY

Designator: N/A

Item #: 11.5-995

 

CO-037A Jan 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, RECTANGULAR FAMILY PACKAGE

Item 11-1042

MO-153H Jan 2024 view
Definition of “Low-Halogen” For Electronic Products

This standard provides terms and definitions for “low-halogen” electronic products.

JS709D Jan 2024 view
DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers.

JESD308A Jan 2024 view
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs). These DDR5 Clocked Unbuffered DIMMs (CUDIMMs) are intended for use as main memory when installed in Computers.

JESD323 Jan 2024 view
DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification

This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Clocked Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CSODIMMs). These DDR5 CSODIMMs are intended for use as main memory when installed in Computers, laptops and other systems.

JESD324 Jan 2024 view
PLASTIC DUAL SMALL OUTLINE, SURFACE TERMINAL, WETTABLE FLANK PACKAGE

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04

 

Item: 11-1044

Cross Reference: DR4.8, DR4.16, DR4.20

MO-340D Dec 2023 view
Serial Interface for Data Converters

This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document.

JESD204D Dec 2023 view
JEDEC Module Sideband Bus (SidebandBus)

This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages.

JESD403-1C Dec 2023 view
XFM Device, Version 2.0

This standard specifies the mechanical and electrical characteristics of the XFM removable memory Device.

JESD233A Dec 2023 view

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