Recently Published Documents

Title Document # Date Details
UNIVERSAL FLASH STORAGE (UFS) HOST PERFORMANCE BOOSTER (HPB) EXTENSION, VERSION 2.0

This standard specifies the extension specification of the UFS electrical interface and the memory device. This document describes the extended feature, called Host Performance Booster (HPB), in UFS specification. It also provides some details in how to utilize the HPB for realizing high performance in UFS devices. Committee item 138.34

JESD220-3A Sep 2020 view
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements

This standard establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. The data is held in an XML format, conforming to an XML schema that this document describes. Get the XML Schema: JEP181_Schema_R1p0

JEP181 Sep 2020 view
UNIVERSAL FLASH STORAGE, UFS 2.2

The purpose of this standard is definition of a UFS Universal Flash Storage electrical interface and a UFS memory device. This standard defines a unique UFS feature set and includes the feature set of eMMC standard as a subset. This standard replaces JESD220C, UFS 2.1, and introduces a feature called WriteBooster.  Item 138.88.

JESD220C-2.2 Aug 2020 view
REGISTRATION - Upper PoP, Plastic Bottom Grid Array Ball, 0.40 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p40...
Item: 11.11-976, Access STP File for MO-344A

Cross Reference: DR4.18

MO-344A Aug 2020 view
BYTE ADDRESSABLE ENERGY BACKED INTERFACE

The purpose of this standard is definition of an energy backed byte addressable function on a nonvolatile dual in-line memory module (NVDIMM). This standard defines the feature set and commands implemented by the energy backed byte addressable function on the NVDIMM.  This standard is used in conjunction with JESD248.  Item 2233.54F

* A minor editorial change has been made to the table under 8.1.3.2, on page 47 on 9/1/2020, from the original posted version 8/18/2020. If you downloaded prior to 9/1/2020, please discard and use the current version.

JESD245D Jul 2020 view
UFS Card Socket Performance Standard

For UFS Card 6 Gb/sItem 11.14-195S

PS-004A Jul 2020 view
Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch, Rectangular Family Package

Designator: PBGA-B#[#]_I0p5...
Item: 11.11-977, Access STP File for MO-276O

Cross Reference: DR4.5

MO-276O Jul 2020 view
DDR5 SDRAM

This document defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8Gb through 32Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3 & LPDDR4 standards (JESD79, JESD79-2, JESD79-3 & JESD209-4). Item 1848.99G.

JESD79-5 Jul 2020 view
TEMPERATURE GRADE AND MEASUREMENT SPECIFICATIONS FOR COMPONENTS AND MODULES

This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Item 1855.01A

JESD402-1 Jul 2020 view
PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1

Definition of PMIC5000, PMIC5010 Voltage Regulator Device for Memory Module Applications

JESD301-1 Jun 2020 view
STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm

JEP106BB Jun 2020 view
Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card E, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.17B.

MODULE4.20.26.E Jun 2020 view
Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.29A.

MODULE4.20.26.B Jun 2020 view
Annex G, Raw Card G, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This annex defines the electrical and mechanical requirements for Raw Card G, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item No. 2228.34C

MODULE4.20.25.G May 2020 view
Annex E, R/C E, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card E, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.33C.

MODULE4.20.25.E May 2020 view
Annex C, R/C C, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This annex defines the electrical and mechanical requirements for Raw Card C, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.31B

MODULE4.20.25.C May 2020 view
1.05 V CMOS

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01

JESD8-34 Apr 2020 view
PRECONDITIONING OF NONHERMETIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING

This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow).

JESD22-A113I Apr 2020 view
288 PIN DDR5 U/R/LR DIMM, 0.85 MM PITCH.

Designator: PDMA-N288-I0p85-R133p8x5p57Z31p8R2p55x0p6
Item: 11.14-197, Access STP Files for MO-329B
Cross Reference: SO-023, GS-010C

MO-329B Apr 2020 view
Registration - Plastic Dual Small Outline Surface, 2 Terminal, Wettable Flank Package

Designator: PDSO-N2-I#-R#x#Z#-CturET0p04
Item: 11.11-970, Access STP File for MO-343A
Cross Reference: DG4.20

MO-343A Mar 2020 view
Addendum No. 1 to JESD79-4, 3D STACKED DRAM

This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58F

JESD79-4-1A Mar 2020 view
Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package

Designator: PBGA-B#[#]_I0p80...
Item: 11.11-971, Access STP Files for MO-210P
Cross Reference: DG4.5

MO-210P Mar 2020 view
EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NON VOLATILE MEMORY DEVICES

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.59 and 19-395.

JESD251A Feb 2020 view
GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES

This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches.

JEP180 Feb 2020 view
SPD5118, SPD5108 HUB AND SERIAL PRESENCE DETECT DEVICE STANDARD

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a master host bus. The designations SPD5118 and SPD5108 refer to the families of devices specified by this document. The term SPD5 Hub refers generically to both devices in the family. Committee Item 1852.07F.

JESD300-5 Feb 2020 view
Registration - Plastic Bottom Ball Grid Array, 0.75 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p75...
Item: 11.11-979, Access STP File for MO-328B
Cross Reference: DR4.5

MO-328B Feb 2020 view
Registration - Plastic Bottom Grid Array Ball, 0.80 mm X 0.65 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p65...
Item: 11.11-970, Access STP File for MO-311E
Cross Reference: DR4.5

MO-311E Feb 2020 view
CUSTOMER NOTIFICATION PROCESS FOR DISASTERS

This standard establishes the requirements for timely notification to affected customers after a disaster has occurred at a supplier’s facility that will affect the committed delivery of product. This standard puts specific emphasis on notification, timing, and notification content which includes risk exposure, impact analysis, and recovery plans. This standard is applicable to suppliers of, and affected customers for, solid-state products and the constituent components used within.

JESD246A Jan 2020 view
Registration - Plastic Bottom Grid Array Ball, 0.65 mm Pitch Square Family Package

Designator: PBGA-B#[#}_I0p65
Item: 11.11-978, Access STP Files for MO-342A
Cross Reference: DR4.5

MO-342A Jan 2020 view
LOW POWER DOUBLE DATA RATE 4 (LPDDR4)

This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3). Committee Item: 1847.22

JESD209-4C Jan 2020 view
DDR4 SDRAM STANDARD

This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78F

JESD79-4C Jan 2020 view
HIGH BANDWIDTH MEMORY (HBM) DRAM

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet. Committee item 1797.99K.

JESD235C Jan 2020 view
POWER AND TEMPERATURE CYCLING

The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes and simultaneously the operating biases are periodically applied and removed. It is intended to simulate worst case conditions encountered in application environments. The power and temperature cycling test is considered destructive and is only intended for device qualification. This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures.

JESD22-A105D Jan 2020 view
MARK LEGIBILITY

This standard describes a nondestructive test to assess solid state device mark legibility. The specification applies only to solid state devices that contain markings, regardless of the marking method. It does not define what devices must be marked or the method in which the device is marked, i.e., ink, laser, etc. The standard is limited in scope to the legibility requirements of solid state devices, and does not replace related reference documents listed in this standard.

JESD22-B114B Jan 2020 view
LOW POWER DOUBLE DATA RATE (LPDDR5)

This document defines the LPDDR5 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5 device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3) and LPDDR4 (JESD209-4). Item 1854.99A

JESD209-5A Jan 2020 view
UNIVERSAL FLASH STORAGE (UFS), Version 3.1

This document replaces all past versions, however JESD220D, January (V 3.0), is available for reference only.The purpose of this standard is definition of an UFS Universal Flash Storage electrical interface and an UFS memory device. This standard defines a unique UFS feature set and includes the feature set of e·MMC Specification as a subset. This standard references also several other standard specifications by MIPI (M-PHY and UniPro Specifications) and INCITS T10 (SBC, SPC and SAM Standards) organizations.  For more information about how to access and download the MIPI specifications related to UFS, visit: https://www.mipi.org/mipi-jedec/DocumentRequestWelcome. Item 135.99

JESD220E Jan 2020 view
Annex A, R/C A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card A, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2231.38(E).

MODULE4.20.26.A Jan 2020 view
Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2149.53.

MODULE4.20.28.B Jan 2020 view
Annex A: Differences between JESD21C Release 29 and its predecessor JESD21C, Release 28.

This table briefly describes the changes made to this standard, JESD21-C, Release 29, compared to its predecessor, JESD21C, Release 28.

AnnexA - JESD21C Jan 2020 view
Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card E, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2149.52

MODULE4.20.28.E Jan 2020 view
Registration - Plastic Dual Connector

Designator: PDXC-PP2-I8p9-R107p6xp15Z26p0-DD2p95x1p1 
Item: 11.14-194, Access STP Files for SO-025A
Cross Reference: TBD

SO-025A Jan 2020 view
Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package

Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11.11-959

MO-341A Oct 2019 view
Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11.11-974, Access STP Files for MO-340A
Cross Reference: DR4.8, DR4.16, DR4.20

MO-340A Oct 2019 view
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.

JEP162A Sep 2019 view
Registration - Plastic Bottom Flatpack 28 Terminal Package

Item 11-11.975, Access STP File for MO-339A

MO-339A Sep 2019 view
Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package

Item 11.11-973, Access STP Files for MO-338A

MO-338A Sep 2019 view
DESCRIPTIVE DESIGNATION SYSTEM FOR ELECTRONIC-DEVICE PACKAGES

This standard establishes requirements for the generation of electronic-device package designators for the JEDEC Solid State Technology Association. The requirements herein are intended to ensure that such designators are presented in as uniform a manner as practicable. Item 11.2-962.

JESD30I Aug 2019 view
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This specification defines the electrical and mechanical requirements for the 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs are intended for use as main memory when installed in PCs. Item 2241.13A

MODULE4.20.26 Aug 2019 view
260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This document defines the electrical and mechanical requirements for 260 pin, 1.2 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops and other systems. This document also contains the DDR4 DIMM Label, Ranks Definition. Item 2224.13A

MODULE4.20.25 Aug 2019 view
SPD Annex L, Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 4

This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 4. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01G. This is an editorial revision to the publication in January 2017.

SPD4.1.2.L-4 Aug 2019 view

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