Recently Published Documents

This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests.

This standard specifies the general requirements of a statistical process control (SPC) system. This is a revision of JESD557C.

This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence.

This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria.

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard.

Terminology update.  

This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash.

This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems.

Designator: N/A
Item: 11.5-1001, Access STP File for CO-038A
Cross Reference: N/A

This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing.

Item 1600.41, Terminology Update  This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics RandomAccess Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices.

Terminology update.  This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

Terminology update.  This document establishes an interface standard for the data path and control plane interface functions for an RFIC component and/or a BBIC component.

Terminology update.   Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications

Terminology update.  This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC).

This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL™-attached memory modules.The purpose is to provide certain reference base targets for CXL™-attached memory modules to enable system design simplification, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Designator: PBGA-B#[#}_I0p4...
Item: 11.11-1006E (Minor editorial Change), Access STP File for MO-352A.01
Cross Reference: N/A

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model.

For more information visit the main JEP30 webpage.

This download includes all files under the parent schema JEP30-10v2-0-0 (Committees: JC-11, JC-11.2) including:

• JEP30-A101v2-0-0 (Assembly Process),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-E101v2-0-0 (Electrical),
  
  • Committees: JC-11, JC-11.2, JC-16
• JEP30-P101v2-0-0 (Package),
  
  • Committees: JC-11, JC-11.2
• JEP30-S101v1-0-0 (Supply Chain),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-T101v2-0-0 (Thermal)
  
  • Committees: JC-11, JC-11.2, JC-15
• JEP30-D10v2-0-0 (Types Dictionary)
  
  • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts.  This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model.

For more information visit the main JEP30 webpage.

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD03 Device ID is DID = 0x0053.

This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality.

This document provides guidelines for evaluating gate reliability and lifetime testing for silicon carbide (SiC) based power devices with a gate oxide or gate dielectric.

(Terminology update.)  This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications.