Recently Published Documents

Title Document # Date Details
Graphics Double Data Rate 7 SGRAM Standard (GDDR7)

This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.

JESD239 Feb 2024 view
PART MODEL SCHEMAS

This download includes all files under the parent schema JEP30-10v5-0-0 (Committees: JC-11, JC-11.2) including:

  • JEP30-A101v2-0-2 (Assembly Process),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-E101v3-0-1 (Electrical),
    • Committees: JC-11, JC-11.2, JC-16
  • JEP30-P101v5-0-0 (Package),
    • Committees: JC-11, JC-11.2
  • JEP30-S101v1-0-2 (Supply Chain),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-T101v2-0-2 (Thermal)
    • Committees: JC-11, JC-11.2, JC-15
  • JEP30-D10v3-0-1 (Types Dictionary)
    • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

JEP30-10v5-0-0 Feb 2024 view
Part Model Package Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-P100D Feb 2024 view
Part Model Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure.

For more information visit the main JEP30 webpage.

JEP30D Feb 2024 view
Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-E100D Feb 2024 view
DDR5 Clock Driver Definition (DDR5CKD01)

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5,
3= Clock Driver, 1= rev 01)

JESD82-531A.01 Feb 2024 view
Registration - Plastic Multi Small Outline, 17 Terminal, 1.20 mm Pitch Package. PMSO-E17.

Package Designator: PMSO-E17_I1p2...

Item 11.11-1046, 

MO-332B Jan 2024 view
SHIPPING AND HANDLING TRAY FOR DDR5 SODIMM MICROELECTRONIC ASSEMBLY

Designator: N/A

Item #: 11.5-995

 

CO-037A Jan 2024 view
STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

JEP106BI Jan 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, RECTANGULAR FAMILY PACKAGE

Item 11-1042

MO-153H Jan 2024 view
Definition of “Low-Halogen” For Electronic Products

This standard provides terms and definitions for “low-halogen” electronic products.

JS709D Jan 2024 view
MARKING, SYMBOLS, AND LABELS OF LEADED AND LEAD-FREE TERMINAL FINISHED MATERIALS USED IN ELECTRONIC ASSEMBLY

This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd  level terminal finish or material.

J-STD-609C Jan 2024 view
DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers.

JESD308A Jan 2024 view
DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs). These DDR5 Clocked Unbuffered DIMMs (CUDIMMs) are intended for use as main memory when installed in Computers.

JESD323 Jan 2024 view
JEDEC® Memory Module Label – for Compute Express Link® (CXL®)

This standard defines the labels that shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format.

JESD405-1A Jan 2024 view
DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification

This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Clocked Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CSODIMMs). These DDR5 CSODIMMs are intended for use as main memory when installed in Computers, laptops and other systems.

JESD324 Jan 2024 view
PLASTIC DUAL SMALL OUTLINE, SURFACE TERMINAL, WETTABLE FLANK PACKAGE

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04

 

Item: 11-1044

Cross Reference: DR4.8, DR4.16, DR4.20

MO-340D Dec 2023 view
Serial Interface for Data Converters

This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document.

JESD204D Dec 2023 view
JEDEC Module Sideband Bus (SidebandBus)

This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages.

JESD403-1C Dec 2023 view
MCP and Discrete e•MMC, e•2MMC, and UFS

Item 142.12.

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

 

MCP3.12.1 Dec 2023 view
Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices

This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices.

JEP150A Dec 2023 view
XFM Device, Version 2.0

This standard specifies the mechanical and electrical characteristics of the XFM removable memory Device.

JESD233A Dec 2023 view
Power Cycling

This Test Method establishes a uniform method for performing solid state device package power cycling stress test.

JESD22-A122B Nov 2023 view
Compression Attached Memory Module (CAMM2) Common Standard

This standard defines the electrical and mechanical requirements for Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LPDDR5/5X SDRAM CAMM2s).

JESD318 Ver. 1.02 Nov 2023 view
Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature

This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation.

JESD22-B112C Nov 2023 view
IC LATCH-UP TEST

This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress.

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880.

JESD78F.02 Nov 2023 view
Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications

This test method covers X-ray imaging for terrestrial applications on packaged devices.

JESD22-B121 Nov 2023 view
Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension

This standard specifies the extension specification of the UFS electrical interface and the memory device.

PLEASE NOTE: Revision and renumbering of JESD231 Version 1.0, August 2022

JESD220-4 Version 1.01 Nov 2023 view
Zoned Storage for UFS

The purpose of this standard is to describe Zoned Storage for UFS, which enables higher bandwidth, lower latency and to reduce write amplification.

JESD220-5 Nov 2023 view
DESCRIPTIVE DESIGNATION SYSTEM FOR ELECTRONIC-DEVICE PACKAGES

This standard establishes requirements for the generation of electronic-device package designators.

JESD30L Nov 2023 view
Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices

This publication provides guidance to SiC product suppliers and related power electronic industries in their evaluation of bipolar degradation mechanism in SiC power devices.

JEP197 Nov 2023 view
Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices

This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches.

JEP198 Nov 2023 view
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema

In conjunction with JEP181A, for user support this file is the entire “XML Requirements Schema”.

JEP181_Schema_R2p0 Nov 2023 view
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements

This publication establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format.

JEP181A Nov 2023 view
A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces

This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces.

JEP196 Nov 2023 view
JEDEC Manual of Organization and Procedure

This Manual sets forth the mission and requirements of JEDEC as an independent incorporated Association governed by a Board of Directors.

 

JM21V Nov 2023 view
Design Requirements - BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM

BALL GRID ARRAY PACKAGE
BALL PITCH ≤ 0.80 MM
BODY SIZES ≤ 21 MM

Item 2-1038

DR-4.5O Nov 2023 view
Registration - PLASTIC DUAL UPPER TO BOTTOM, 1.38 MM X1.00 MM PITCH CONNECTOR (CMT)

Designator: SO-032B_PDUtBXC-H644_I1p0-R17p15x78p0Z1p05
Item: 14-222
Cross Reference: N/A

SO-032B Nov 2023 view
Registration - 288 TERM DDR5 DIMM, 0.85 MM PITCH, MICROELECTRONIC ASSEMBLY

Designator: PDMA-N288-I0p85-R133p8x#p#7Z31p8R2p55x0p6

Item: 11.14-221, Access 

Cross Reference: MO-329, SO-023, GS-010

 

MO-329G Nov 2023 view
PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)

This standard facilitates the procurement and use of semiconductor die products provided in bare or bumped die form, and provides requirements and guidance to die suppliers as to the levels of as-delivered performance, quality and reliability expected. It also reflects the special needs of die product customers in terms of design and application data.

JESD49B.01 Oct 2023 view
JEDEC COMMITTEE SCOPE MANUAL

The JEDEC Board of Directors is responsible for establishing appropriate committees to conduct its standardization activities.  This publication identifies the service and product committees established by the Board of Directors and defines their scopes.

JM18U Oct 2023 view
DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS

This publication describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels.

JESD400-5B Oct 2023 view
DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH MICROELECTRONIC ASSEMBLY

Designator:  XBNA-N#_I1p0_...

Item No:  14-218

MO-358A Sep 2023 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2.00 MM PITCH, RECTANGULAR PACKAGE

Designator:  H-PDSO-G12_12p0-12p0x9p4Z2p8

Item No: 11-1034

 

 

MO-359A Sep 2023 view
DDR5 DIMM Labels

The following labels shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently.

JESD401-5B Aug 2023 view
Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This revision is to add R/C K1 for up to
PC4-3200 support for the DDR4 SO-DIMM R/C K Annex. Item 2228.68.

MODULE4.20.25.K.01 Aug 2023 view
TS511X, TS521X Serial Bus Thermal Sensor Device Standard

This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document.

JESD302-1A Aug 2023 view
REGISTRATION - Upper PoP, Plastic Bottom Grid Array Ball, 0.40 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p40...
Item: 11.11-1035, Access 

Cross Reference: DR4.18

MO-344B Aug 2023 view
PLASTIC QUAD FLATPACK 1.27 MM PITCH, 5.00 MM X 6.00 MM RECTANGULAR FAMILY PACKAGE

Designator: PQFP-B#[#]_Ip27...

Item #: 11-1037 

MO-356A Aug 2023 view
LPDDR5 CAMM2, 1.38 MM X 1.00 MM PITCH MICROELECTRONIC ASSEMBLY

Designator: XBMA-H644_I1p0_R78p0x23p0Z2p6

Item #:  11.14-219

MO-357A Aug 2023 view

Pages