Recently Published Documents

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

This download includes all files under the parent schema JEP30-10v3-0-0 (Committees: JC-11, JC-11.2) including:

• JEP30-A101v2-0-1 (Assembly Process),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-E101v2-0-1 (Electrical),
  
  • Committees: JC-11, JC-11.2, JC-16
• JEP30-P101v3-0-0 (Package),
  
  • Committees: JC-11, JC-11.2
• JEP30-S101v1-0-1 (Supply Chain),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-T101v2-0-1 (Thermal)
  
  • Committees: JC-11, JC-11.2, JC-15
• JEP30-D10v3-0-0 (Types Dictionary)
  
  • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

This standard establishes requirements for the generation of electronic-device package designators for the JEDEC Solid State Technology Association. The requirements herein are intended to ensure that such designators are presented in as uniform a manner as practicable. Item 11.2-1031S.

NOTE IF YOU DOWNLOADED THIS DOCUMENT PRIOR TO 12/16/2022 PLEASE DISCARD AND VIEW AGAIN, PREVIOUS VERSION CONTAINED FORMAT ISSUES.

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

Designator: PBGA-B#[#]I0p5...

Item JC11.11-1036

Cross Reference: DR4.5

Designator: PQFP-B#[#]_Ip27...

Item #: 11-1037 - STP files to follow

Designator: N/A

Item #: 11.5-1033 - STP file to follow

This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document.

This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data.

Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits

This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories

Designator: PQFP-B#[#]_I0p65...

Item: 11-981E, Access STP Files for MO-346A

Cross Reference: N/A

This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests.

This standard specifies the general requirements of a statistical process control (SPC) system. 
This is a revision of JESD557C.

This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence.

This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria.

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CK01 Device ID is DID = 0x0531. (5 = DDR5, 3= Clock Driver, 1= rev 01).

Terminology update.  

This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash.

This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems.

Designator: N/A
Item: 11.5-1001, Access STP File for CO-038A
Cross Reference: N/A

This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing.

Item 1600.41, Terminology Update  

This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics Random

Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices.

Terminology update.  

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

Terminology update.  

This document establishes an interface standard for the data path and control plane interface functions for an RFIC component and/or a BBIC component.

Terminology update.   

This legacy document is a comprehensive users’ guide for silicon rectifier diode applications.