Recently Published Documents

Title Document # Date Details
JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)

This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC).

JESD319 Sep 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, 0.95 MM PITCH, RECT PACKAGE (TRANSISTOR)

Item #: 11-1067

Package Designator: PDSO-G3(6)-i0p95....

TO-236-I Sep 2024 view
DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS

This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels.

JESD400-5C Sep 2024 view
JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®)

This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later.

JESD325 Sep 2024 view
Temperature Range and Measurement Standards for Components and Modules

This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications.

JESD402-1B Sep 2024 view
Foundry Process Qualification Guidelines – Technology Qualification Vehicle Testing (Wafer Fabrication Manufacturing Sites)

The publication provides methodologies for measurements to qualify a new semiconductor wafer process.

JEP001-3B Sep 2024 view
PLASTIC DUAL FLANGE MOUNT, 2.00 MM PITCH RECT PACKAGE (TRANSISTOR)

Item #11-1060

Package Designator:  PDFM-E5_I2p0....

TO-283A Sep 2024 view
PLASTIC MULTI SMALL OUTLINE, 1.20 MM PITCH PACKAGE 1.14 MM PITCH, 15.40 MM BODY WIDTH, RECT FAMILY PACKAGE

Item: 11-1065

Designator: PMSO-E#_I1p14-...

MO-354B Sep 2024 view
PLASTIC BOTTOM GRID ARRAY BALL, 0.80 MM PITCH, SQUARE FAMILY PACKAGE

Designator: PBGA-B#[#]_I80...

Item: 11-1064

 

Cross Reference: DR4.5

MO-216H Sep 2024 view
PART MODEL SCHEMAS

This download includes all files under the parent schema JEP30-10v6-0-0 (Committees: JC-11, JC-11.2) including:

  • JEP30-A101v2-0-3 (Assembly Process),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-E101v4-0-0 (Electrical),
    • Committees: JC-11, JC-11.2, JC-16
  • JEP30-P101v6-0-0 (Package),
    • Committees: JC-11, JC-11.2
  • JEP30-S101v1-0-3 (Supply Chain),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-T101v2-0-3 (Thermal)
    • Committees: JC-11, JC-11.2, JC-15
  • JEP30-D10v4-0-1 (Types Dictionary)
    • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

JEP30-10v6-0-0 Aug 2024 view
Part Model Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure.

For more information visit the main JEP30 webpage.

JEP30E Aug 2024 view
Part Model Assembly Process Classification Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts.  This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-A100B Aug 2024 view
Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-E100E Aug 2024 view
PLASTIC DUAL SMALL OUTLINE, RECTANGULAR FAMILY PACKAGE

Package Designator: PDSO-G#-I##....

Item# -  JC11.11-1069

MO-153I Aug 2024 view
SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD

Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser.  Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32

JESD218B.03 Aug 2024 view
Guidelines for Reverse Recovery Time and Charge Measurement of SiC MOSFET Version 1.0

This guideline is intended to overcome the limitations of prior standards and provide a test circuit and method that provides both reliable and repeatable results.

JEP201 Aug 2024 view
PLASTIC DUAL FLATPACK, SURFACE TERMINAL, 1.27 MM PITCH RECTANGULAR FAMILY PACKAGE

Designator:PDFN-N[#]_I1p27...

Item #: 11-1063

 

MO-364A Aug 2024 view
JEDEC Module Sideband Bus (SidebandBus)

This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages.

JESD403-1C.01 Aug 2024 view
Part Model Package Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-P100E Aug 2024 view
Part Model Thermal Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-T100B Aug 2024 view
Part Model Supply Chain Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-S100A Aug 2024 view
LPDDR5 CAMM2 Connector Performance Standard

LPDDR5 CAMM2 Connector Performance Standard

PS-007A Jul 2024 view
PLASTIC BOTTOM GRID, ARRAY BALL, 0.60 MM X 0.50 MM PITCH RECTANGULAR FAMILY PACKAGE

Designator: PBGA-B#[#]_I0p5...

Item #: 11-1066

MO-363A Jul 2024 view
STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

JEP106BJ.01 Jul 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2.00 MM PITCH, RECTANGULAR PACKAGE

Designator:  H-PDSO-G12_12p0-12p0x9p4Z2p8

Item No: 11-1049

 

 

MO-359B Jul 2024 view
Descriptive Designation System for Electronic-device Packages and Footprints

This standard establishes requirements for the generation of electronic-device package designators.

JESD30M Jul 2024 view
Style Manual for Standards and Other Publications of JEDEC

This manual establishes requirements for the preparation of standards and certain other publications of the JEDEC Solid State Technology Association.

JM7A Jul 2024 view
DDR5 SDRAM

Version 1.31

This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4).

JESD79-5C.01 Jul 2024 view
PLASTIC FLANGE MOUNT, THROUGH-HOLE, 2.54 MM PITCH RECT PACKAGE (TRANSISTOR)

Package Designator:  PMDF-T5_I2p54...

Item # 11-1058

TO-282A Jun 2024 view
MCP and Discrete e•MMC, e•2MMC, and UFS

Item 142.12

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

 

MCP3.12.1-1 Jun 2024 view
LPDDR5/5X Serial Presence Detect (SPD) Contents

This publication describes the serial presence detect (SPD) values for all LPDDR5/5X memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non-volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding.

JESD406-5 Jun 2024 view
PLASTIC DUAL UPPER TO BOTTOM, 1.38 MM X1.00 MM PITCH CONNECTOR (CMT)

Designator: SO-032B_PDUtBXC-H644_I1p0-R17p15x78p0Z1p05
Item: 14-227
Cross Reference: N/A

SO-032C Jun 2024 view
LPDDR5 CAMM2, 1.38 MM X 1.00 MM PITCH MICROELECTRONIC ASSEMBLY

Designator: XBMA-H644_I1p0_R78p0x23p0Z2p6

Item #:  14-228

MO-357C Jun 2024 view
DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH, MICROELECTRONIC ASSEMBLY

Designator:  XBNA-N#_I1p0_...

Item No:  14-229

MO-358B Jun 2024 view
Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1

This document provides guidelines for test methods and circuits to be used for measuring switching energy loss due to output capacitance hysteresis in semiconductor power devices.

JEP200 Jun 2024 view
JEDEC® Memory Module Label – for Compute Express Link® (CXL®)

This standard defines the labels that shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format.

JESD405-1B Jun 2024 view
288 TERM DDR5 DIMM, 0.85 MM PITCH, MICROELECTRONIC ASSEMBLY

Designator: PDMA-N288-I0p85-R133p8x#p#7Z31p8R2p55x0p6

Item: 11.14-224, Access 

Cross Reference: MO-329, SO-023, GS-010

 

MO-329H.01 Jun 2024 view
Board Level Drop Test Method of Components for Handheld Electronic Products

This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components.

JESD22-B111A.01 Jun 2024 view
Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA)

This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices.

JEP170A Jun 2024 view
Information Requirements for the Qualification of Solid State Devices

This standard defines the requirements for the device qualification package, which the supplier provides to the customer.

JESD69D Jun 2024 view
Low Power Double Data Rate 4 (LPDDR4)

This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb.

JESD209-4E Jun 2024 view
DDR5 Registering Clock Driver Definition (DDR5RCD04)

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054.

JESD82-514.01 Jun 2024 view
DDR5 DIMM Labels

This standard defines the labels that shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently.

JESD401-5B.01 May 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, RECTANGULAR PACKAGE

Item 11-1051

Package Designator:  PDSO-G#_...

MO-203D May 2024 view
PLASTIC BOTTOM GRID, ARRAY BALL, 0.50 MM X 0.70 MM PITCH RECTANGULAR FAMILY PACKAGE

Item #11-1048A

Package Designator: PBGA-B#[#] I0p5...

MO-360A May 2024 view
PLASTIC QUAD FLATPACK, 28 TERMINAL PACKAGE

Item 11-1054

Package Designator: PQFP-N28_I4p0...

MO-339B May 2024 view
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE)

Package Designator: P-PDSO-G2...

DO-215-E May 2024 view
Graphics Double Data Rate 7 SGRAM Standard (GDDR7)

This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.  

ATTENTION USERS: Be advised that the formulating subcommittee is working on an update that may require host design changes. Members of the subcommittee may contact the TG for more information.

JESD239.01 Apr 2024 view
Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly

This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd  level terminal finish or material.

J-STD-609C.01 Apr 2024 view
SHIPPING AND HANDLING TRAY FOR LPDDR5 CAMM2 MODULE

Item #11.5-1057

CO-041A Apr 2024 view

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