Recently Published Documents

Title Document # Date Details
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1.

JS-002-2022 Jun 2023 view
GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTS

This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests.

JEP142 May 2023 view
Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification

This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing.

JEP114A May 2023 view
Statistical Process Control Systems

This standard specifies the general requirements of a statistical process control (SPC) system. This is a revision of JESD557C.

JESD557D May 2023 view
Graphics Double Data Rate (GDDR6) SGRAM Standard

This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212).

JESD250D May 2023 view
HYBRIDS/MCM

This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence.

JESD93A May 2023 view
NAND Flash Interface Interoperability

This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations.

JESD230F.01 May 2023 view
Guidelines for Supplier Performance Rating

This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria.

JEP146B May 2023 view
DDR5 Clock Driver Definition (DDR5CK01)

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CK01 Device ID is DID = 0x0531. (5 = DDR5, 3= Clock Driver, 1= rev 01).

JESD82-531 May 2023 view
SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard.

JESD300-5B.01 May 2023 view
STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

JEP106BG May 2023 view
DDR4 NVDIMM-N Design Standard

Terminology update.  

This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash.

JESD248A.01 Apr 2023 view
STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:

This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process.

JESD63 Apr 2023 view
STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALS

This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems.

JESD87 Apr 2023 view
Registration - Shipping and Handling Tray for M.2 Type 2230 Microelectronic Assembly

Designator: N/A
Item: 11.5-1004, Access STP File for CO-039A
Cross Reference: N/A

CO-039A Apr 2023 view
Registration - Shipping and Handling Tray for M.2 Type 2280 SSD Microelectronic Assembly

Designator: N/A
Item: 11.5-1001, Access STP File for CO-038A
Cross Reference: N/A

CO-038A Apr 2023 view
PMIC50x0 Power Management IC Standard

This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device asused for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

JESD301-1A.02 Rev. 1.8.5 Apr 2023 view
Temperature Cycling

This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing.

JESD22-A104F.01 Apr 2023 view
Registration - Plastic Quad Flat Package, Gull Wing and J-Lead, 0.65 MM Pitch

Designator: PQFP-E#_I0p65-R...
Item: 11.11-1028, Access STP File for MO-355A
Cross Reference: N/A

MO-355A Apr 2023 view
Graphics Double Data (GDDR4) SGRAM Standard

Item 1600.41, Terminology Update  This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics RandomAccess Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices.

SDRAM3.11.5.8 R16.01 Mar 2023 view
Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS

Item 140.07B.

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

 

MCP3.12.1 Mar 2023 view
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications

Terminology update.  This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

JESD82-27.01 Mar 2023 view
Fully Buffered DIMM Design for Test, Design for Validation (DFx)

Terminology update.  This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology.

JESD82-28A.01 Mar 2023 view
RADIO FRONT END - BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE

Terminology update.  This document establishes an interface standard for the data path and control plane interface functions for an RFIC component and/or a BBIC component.

JESD207.01 Mar 2023 view
COMPACT THERMAL MODEL OVERVIEW

Terminology update.This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents.

JESD15-1.01 Mar 2023 view
DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS

Terminology update.   Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications

JESD82-13A.01 Mar 2023 view
SILICON RECTIFIER DIODES:

Terminology update.   This legacy document is a comprehensive users’ guide for silicon rectifier diode applications.

JESD282B.02 Mar 2023 view
RADIO FRONT END - BASEBAND (RF-BB) INTERFACE

Terminology update.  This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC).

JESD96A.01 Mar 2023 view
GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD

Terminology update.  

This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package

JESD232A.01 Mar 2023 view
Compute Express Link (CXL™) Memory Module Base Standard

This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL™-attached memory modules.The purpose is to provide certain reference base targets for CXL™-attached memory modules to enable system design simplification, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

JESD317 Mar 2023 view
Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package

Designator: PBGA-B#[#]_I0p... 
Item: 11.11-988, Access STP Files for MO-210R
Cross Reference: DG4.5
https://www.jedec.org/filebrowser/download/1625

MO-210R Mar 2023 view
Registration - Plastic Bottom Grid Array Ball, 0.40 MM Pitch Rectangular Family Package

Designator: PBGA-B#[#}_I0p4...
Item: 11.11-1006E (Minor editorial Change), Access STP File for MO-352A.01
Cross Reference: N/A

MO-352A.01 Mar 2023 view
DDR5 DIMM Labels

This standard for labels applies to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format, Item 2268.02C

JESD401-5A Mar 2023 view
Part Model Electrical Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-E100A Mar 2023 view
Part Model Package Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-P100A Mar 2023 view
Part Model Thermal Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-T100A Mar 2023 view
Part Model SupplyChain Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-S100 Mar 2023 view
PART MODEL SCHEMAS

This download includes all files under the parent schema JEP30-10v2-0-0 (Committees: JC-11, JC-11.2) including:

  • JEP30-A101v2-0-0 (Assembly Process),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-E101v2-0-0 (Electrical),
    • Committees: JC-11, JC-11.2, JC-16
  • JEP30-P101v2-0-0 (Package),
    • Committees: JC-11, JC-11.2
  • JEP30-S101v1-0-0 (Supply Chain),
    • Committees: JC-11, JC-11.2, JC-14
  • JEP30-T101v2-0-0 (Thermal)
    • Committees: JC-11, JC-11.2, JC-15
  • JEP30-D10v2-0-0 (Types Dictionary)
    • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

JEP30-10v2-0-0 Mar 2023 view
Part Model Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure.

For more information visit the main JEP30 webpage.

JEP30A Mar 2023 view
Part Model Assembly Process Classification Guidelines for Electronic-Device Packages – XML Requirements

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts.  This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model.

For more information visit the main JEP30 webpage.

JEP30-A100A Mar 2023 view
Compute Express Link (CXL) Memory Module Label

The following labels shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format.

JESD405-1 Feb 2023 view
DDR5 Registering Clock Driver Definition (DDR5RCD03)

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD03 Device ID is DID = 0x0053.

JESD82-513 Feb 2023 view
Annex F, R/C F, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card F, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.43.

MODULE4.20.26.F Feb 2023 view
Guidelines for Packing and Labeling of Integrated Circuits in Unit Container Packing (Tubes, Trays, and Tape and Reel)

This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality.

JEP130C Feb 2023 view
DDR5 Registering Clock Driver Definition (DDR5RCD02)

This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052.

JESD82-512 Feb 2023 view
Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs

This document provides guidelines for evaluating gate reliability and lifetime testing for silicon carbide (SiC) based power devices with a gate oxide or gate dielectric.

JEP194 Feb 2023 view
Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion

This document elaborates on the information given in JEP184 regarding the long-time stability of device parameters under static conditions and under application near switching conditions.

JEP195 Feb 2023 view
DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM APPLICATIONS

(Terminology update.)  This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications.

JESD82-17.01 Feb 2023 view
DEFINITION OF THE SSTU32S869 AND SSTU32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

Terminology update.This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32S869 and SSTU32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

JESD82-12A.01 Feb 2023 view
FBDIMM: ARCHITECTURE AND PROTOCOL

Terminology update. This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5).

JESD206.01 Feb 2023 view

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