Recently Published Documents

Title Document # Date Details
DDR4 NVDIMM-P BUSS PROTOCOL

An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory.  A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K.

JESD304-4 Nov 2020 view
Registration - Plastic Multi Position Flange Mount Mixed Technology, 0.10 in. Pitch Package

Item 11.10-456(E)

TO-220L.01 Nov 2020 view
Annex A, R/C A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card A, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2231.38A.

MODULE4.20.26.A Nov 2020 view
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 6

This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 6. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01H. 

SPD4.1.2.L-6 Nov 2020 view
Registration - Plastic Quad Flatpack, 0.65 mm Pitch, 3.30 mm Body, Square Family Package

Designator: PQFP-B#[#]_I0p65...
Item: 11.11-981, Access STP Files for MO-346A
Cross Reference: N/A

MO-346A Nov 2020 view
UNIVERSAL FLASH STORAGE (UFS) CARD EXTENSION, Version 3.0

This standard specifies the characteristics of the UFS card electrical interface and the memory device. This document defines the added/modified features in UFS card compared to embedded UFS device. For other common features JESD220, UFS, will be referenced.

JESD220-2B Nov 2020 view
CYCLED TEMPERATURE HUMIDITY-BIAS WITH SURFACE CONDENSATION LIFE TEST

The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. The Cycled Temperature-Humidity-Bias Life Test is typically performed on cavity packages (e.g., MQUADs, lidded ceramic pin grid arrays, etc.) as an alternative to JESD22-A101 or JESD22-A110.

JESD22-A100E Nov 2020 view
TEMPERATURE CYCLING

This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling. This standard applies to single-, dual- and triple-chamber temperature cycling and covers component and solder interconnection testing. It should be noted that this standard does not cover or apply to thermal shock chambers. This test is conducted to determine the ability of components and solder interconnects to withstand mechanical stresses induced by alternating high- and low-temperature extremes. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses.

JESD22-A104F Nov 2020 view
CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES

This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle.

JEP167A Nov 2020 view
DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD

Definition for all DDRx component documents to reference. This is generic to any DDRxtechnology. Item 1842.34

JESD404-1 Nov 2020 view
Standard - Plastic Dual Small Outline, 1.27 mm pitch, 7.50 mm Body Width Rectangular Package Family

Designator: PDSO-G#-I1p27...

Item 11.11-967(S).

MS-013G Oct 2020 view
JEDEC MODULE SIDEBAND BUS (SidebandBus)

This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.37C.

JESD403-1 Oct 2020 view
Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick

Designator: PDSO-G#_I0P5-##...
Item: 11.11-984, Access STP Files for MO-345A
Cross Reference: SO-023, GS-010C

MO-345A Oct 2020 view
JEDEC Manual of Organization and Procedure

The mission of JEDEC is to serve the solid state industry by creating, publishing, and promoting global acceptance of standards, and by providing a forum for technical exchange on leading industry topics. This manual provides guidance for JEDEC members and staff to perform their functions correctly in the standardization process.

JM21T Oct 2020 view
UNIVERSAL FLASH STORAGE (UFS) HOST PERFORMANCE BOOSTER (HPB) EXTENSION, VERSION 2.0

This standard specifies the extension specification of the UFS electrical interface and the memory device. This document describes the extended feature, called Host Performance Booster (HPB), in UFS specification. It also provides some details in how to utilize the HPB for realizing high performance in UFS devices. Committee item 138.34

JESD220-3A Sep 2020 view
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements

This standard establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. The data is held in an XML format, conforming to an XML schema that this document describes. Get the XML Schema: JEP181_Schema_R1p0

JEP181 Sep 2020 view
Standard - Plastic Dual Small Outline (SO) Gull Wing, 1.27 mm Pitch Package

Designator: PDSO-G#_I127-##...
Item 11.11-972(E), Minor editorial correction.

MS-012G.02 Sep 2020 view
Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick

Designator: PDSO-G#_I0P##-##...
Item 11.11-983

MO-193F Sep 2020 view
Registration - 12 Pin UFS Card, 0.91 mm Pitch

Designator: PBMA-N11-I0p91-CturZ1p0

Item 11.11-985

MO-320B Sep 2020 view
Registration - Plastic Dual Small Outline Gull Wing Package, 1.45 mm Thick

Item 11.10-458

MO-178D Sep 2020 view
REGISTRATION - 288 PIN DDR5 DIMM SMT, 0.85 MM PITCH SOCKET OUTLINE

Designator: PDXC-LO288-I0p85-R162p0x6p5Z21p3-N5p20S3p1Z0p2
Item: 11.14-202, Access STP Files for SO-023C
Cross Reference: MO-329, GS-010C 

SO-023C Sep 2020 view
Registration - 288 Pin DDR5 DIMM, 0.85 mm Pitch Microelectronic Assembly

Designator: PDMA-N288-I0p85-R133p8x...
Item: 11.14-201, Access STP Files for MO-329C
Cross Reference: SO-023, GS-010C

MO-329C Sep 2020 view
UNIVERSAL FLASH STORAGE, UFS 2.2

The purpose of this standard is definition of a UFS Universal Flash Storage electrical interface and a UFS memory device. This standard defines a unique UFS feature set and includes the feature set of eMMC standard as a subset. This standard replaces JESD220C, UFS 2.1, and introduces a feature called WriteBooster.  Item 138.88.

JESD220C-2.2 Aug 2020 view
Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card E, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2149.34a

MODULE4.20.28.E Aug 2020 view
Annex D, Raw Card D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.08c

MODULE4.20.28.D Aug 2020 view
Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2149.38a.

MODULE4.20.28.B Aug 2020 view
Annex A, R/C A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card A, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.40a.

MODULE4.20.28.A Aug 2020 view
REGISTRATION - Upper PoP, Plastic Bottom Grid Array Ball, 0.40 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p40...
Item: 11.11-976, Access STP File for MO-344A

Cross Reference: DR4.18

MO-344A Aug 2020 view
BYTE ADDRESSABLE ENERGY BACKED INTERFACE

The purpose of this standard is definition of an energy backed byte addressable function on a nonvolatile dual in-line memory module (NVDIMM). This standard defines the feature set and commands implemented by the energy backed byte addressable function on the NVDIMM.  This standard is used in conjunction with JESD248.  Item 2233.54F

* A minor editorial change has been made to the table under 8.1.3.2, on page 47 on 9/1/2020, from the original posted version 8/18/2020. If you downloaded prior to 9/1/2020, please discard and use the current version.

JESD245D Jul 2020 view
UFS Card Socket Performance Standard

For UFS Card 6 Gb/sItem 11.14-195S

PS-004A Jul 2020 view
Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch, Rectangular Family Package

Designator: PBGA-B#[#]_I0p5...
Item: 11.11-977, Access STP File for MO-276O

Cross Reference: DR4.5

MO-276O Jul 2020 view
DDR5 SDRAM

This document defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8Gb through 32Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3 & LPDDR4 standards (JESD79, JESD79-2, JESD79-3 & JESD209-4). Item 1848.99G.

JESD79-5 Jul 2020 view
TEMPERATURE GRADE AND MEASUREMENT SPECIFICATIONS FOR COMPONENTS AND MODULES

This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Item 1855.01A

JESD402-1 Jul 2020 view
PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1

Definition of PMIC5000, PMIC5010 Voltage Regulator Device for Memory Module Applications

JESD301-1 Jun 2020 view
STANDARD MANUFACTURERS IDENTIFICATION CODE

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm

JEP106BB Jun 2020 view
Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card E, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.17B.

MODULE4.20.26.E Jun 2020 view
Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.29A.

MODULE4.20.26.B Jun 2020 view
Annex G, Raw Card G, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This annex defines the electrical and mechanical requirements for Raw Card G, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item No. 2228.34C

MODULE4.20.25.G May 2020 view
Annex E, R/C E, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This specification defines the electrical and mechanical requirements for Raw Card E, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.33C.

MODULE4.20.25.E May 2020 view
Annex C, R/C C, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

This annex defines the electrical and mechanical requirements for Raw Card C, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.31B

MODULE4.20.25.C May 2020 view
1.05 V CMOS

This standard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01

JESD8-34 Apr 2020 view
PRECONDITIONING OF NONHERMETIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING

This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow).

JESD22-A113I Apr 2020 view
Registration - Plastic Dual Small Outline Surface, 2 Terminal, Wettable Flank Package

Designator: PDSO-N2-I#-R#x#Z#-CturET0p04
Item: 11.11-970, Access STP File for MO-343A
Cross Reference: DG4.20

MO-343A Mar 2020 view
Addendum No. 1 to JESD79-4, 3D STACKED DRAM

This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58F

JESD79-4-1A Mar 2020 view
Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package

Designator: PBGA-B#[#]_I0p80...
Item: 11.11-971, Access STP Files for MO-210P
Cross Reference: DG4.5

MO-210P Mar 2020 view
GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES

This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches.

JEP180 Feb 2020 view
EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NON VOLATILE MEMORY DEVICES

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.59 and 19-395.

JESD251A Feb 2020 view
SPD5118, SPD5108 HUB AND SERIAL PRESENCE DETECT DEVICE STANDARD

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a master host bus. The designations SPD5118 and SPD5108 refer to the families of devices specified by this document. The term SPD5 Hub refers generically to both devices in the family. Committee Item 1852.07F.

JESD300-5 Feb 2020 view
Registration - Plastic Bottom Ball Grid Array, 0.75 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p75...
Item: 11.11-979, Access STP File for MO-328B
Cross Reference: DR4.5

MO-328B Feb 2020 view
Registration - Plastic Bottom Grid Array Ball, 0.80 mm X 0.65 mm Pitch Rectangular Family Package

Designator: PBGA-B#[#]_I0p65...
Item: 11.11-970, Access STP File for MO-311E
Cross Reference: DR4.5

MO-311E Feb 2020 view

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