JEDEC NVDIMM-P Workshop

Thursday, October 10 • Santa Clara, CA


Thursday, October 17 • Hsinchu, Taiwan

8:30-9:30AMOnsite check-in for registered attendees
9:30-9:35AM

Welcome & Opening Remarks

Jonathan Hinkle, Lenovo/Program Chair

9:35-10:00AM
 

Overview of System & App Requirements Influencing NVDIMM-P Definition

Presenter: Aaron Nygren, AMD

More details coming soon.

10:00-10:55AM
 

NVDIMM-P Introduction, Overview and Methodology

Presenter: Wendy Elsasser, ARM

This presentation will introduce the audience to the NVDIMM-P protocol, illustrating how the DRAM bus is re-used as well as the changes made to incorporate support of non-volatile media. This includes support for a larger address space, non-deterministic responses, RAS capabilities, additional meta-data, and flow control. The need for persistence and mechanisms incorporated to ensure data integrity across power fail events will also be highlighted.

10:55-11:05AMSession Break
11:05AM-Noon
 

NVDIMM-P Power-on, Initialization and Training, Registers, SPD

Presenter: Tsun Ho Liu, Synopsys

This session will cover NVDIMM-P initialization, interface training and registers for DDR4 and DDR5 NVDIMM-P modules. These modules can share the same channel with DDR4 or DDR5 DIMMs and provide additional training features and capability registers. In order to train the media which is controlled by the NVDIMM-P controller, a specific training flow has been defined. Other aspects of the initialization and interface training will cover the response pins, vref and ODT controls, training pattern configuration, optional DQS interval oscillator etc.

Noon-1:00PMLunch
1:00-2:00PM
 

NVDIMM-P Write/Read Operations, Utilization 

Presenter: Benjamin Lim, Samsung

XREAD; SREAD; Read ID; LENGTH; tRRSE; maxrdcmdcnt; XWRITE; PWRITE; implicit/explicit flush; FLUSH (push to NVM); flush command modes; ordering rules; WGID bitmap (status/flow); management with no-WGID; Persistence management; energy-backed vs. non Utilization; IOP operation; IOP modes; approval power-down/SREF modes, DFS.

2:00-2:55PM

NVDIMM-P Reliability and Optimization Features, MMR and Programming Interface

Presenter: Scott Lee, Microsoft

UNMAP, Sanitization, Other commands (MPC, etc.), Error Handling, MMR, Highlight aspects of other specs (DDR, BAEBI) that have been leveraged.

2:55-3:20PM

DDR5 NVDIMM-P Specifics Preview

Presenter: Frank Ross, Micron Technology

Overview and explanation of the coming DDR5 NVDIMM-P specification and the expanded features supported in that standard for modules compatible in the channel with DDR5 DIMMs.

3:20-3:45PM

DDR5 NVDIMM-P Profiles Overview (Expected Module Types, etc.)

Presenter: Frank Ross, Micron Technology

Introduction to the NVDIMM-P profiles methodology for definition of the common supported features for different implementations of NVDIMM-P.

3:45-4:20PM

Wrap Up

Presenter: Frank Ross, Micron Technology

Program, topics and speakers subject to change without notice.