Global Standards for the Microelectronics Industry
JEDEC Announces Publication of LPDDR3 Standard for Low Power Memory Devices
ARLINGTON, Va., USA – May 17, 2012 – JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD209-3 LPDDR3 Low Power Memory Device Standard, designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. LPDDR3 offers a higher data rate, improved bandwidth and power efficiency, and higher memory densities over its groundbreaking predecessor, LPDDR2. Developed by JEDEC’s JC-42.6 Subcommittee for Low Power Memories, the LPDDR3 Low Power Memory Device Standard is available for free download from the JEDEC website:http://www.jedec.org/standards-documents/results/jesd209-3.
LPDDR3 achieves a data rate of 1600Mbps (versus 1066Mbps for LPDDR2) through the addition of new features, including:
- Write-Leveling and CA Training: These features allow the memory controller to compensate for signal skew, ensuring that data input setup and hold timing as well as command and address input timing requirements are met while operating at the industry’s fastest input bus speeds
- On Die Termination (ODT): This optional feature enables a light termination to LPDDR3 data lanes to improve high-speed signaling with minimal impact on power consumption, system operation and pin count
- Low I/O capacitance