JEDEC Announces New Release of JEP30 Part Model Guidelines, Empowering Chiplet Integration

ARLINGTON, VA., USA – May 30, 2024JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of a new release of the JEP30 PartModel Guidelines, including reference documents and related XML Schema files.  JEP30 and its supporting documents and resources are available for free download from the JEDEC website

A groundbreaking collaboration between the Open Compute Project Foundation (OCP) and JEDEC to enhance JEP30 is combining the capabilities and open standards of OCP’s Chiplet Data Extensible Markup Language (CDXML) into the JEDEC’s JEP30 PartModel Guidelines. This integration expands the capability of the PartModel to enable chiplet builders to also provide standardized chiplet part descriptions to their customers electronically. This advancement opens the door to automating System in Package (SiP) design and assembly using chiplets. The chiplet descriptions encompass crucial information for SiP builders, including thermal properties, physical and mechanical requirements, behavior specifications, power and signal integrity properties, testing in-package and security parameters. JEDEC and OCP extended their collaboration with this latest release by enabling the PartModel to represent Die-Arrays, scalable to support multiple depths of hierarchical nested arrays and billions of bumps intended to support the industry for decades to come.

“The evolution of JEP30 represents a paradigm shift in facilitating electronic product development and manufacturing,” said Mian Quddus, JEDEC Board of Directors Chairman. “Enabling component manufacturers to create standardized digital part models streamlines design processes while reducing human error, marking a transformative leap forward.”

“The OCP is very pleased to continue its collaboration with JEDEC, advancing the standards needed to build a new silicon supply chain in support of commercially viable and standalone Chiplet marketplace, as part of our vision for an Open Chiplet Economy,” said Cliff Grossner, Ph.D., Chief Innovation Officer at OCP.  “The addition of a standard representation for Die-Arrays in just one of the follow- on joint work efforts between the OCP and JEDEC communities and we look forward to a long line of follow on additions to support advanced SiP packaging.”

About JEP30

JEP30 sets the stage for seamless digital part data exchange between manufacturers and end users.  These guidelines show a standardized format compatible across various CAD tools, fostering efficient communication and utilization of part models.  From design to supply chain management, JEP30’s digital twin concept optimizes processes across the product lifecycle.

For all forms of electronic parts, JEP30 guidelines define the XML structure for the assembly process classification, electrical, physical, thermal, material declaration, and supply chain characteristics including product change notices and product discontinuances. The guidelines are designed to be completely scalable to cover components on the market today as well as new parts that emerge in the future.


JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 350 member companies work together in more than 100 JEDEC committees and task groups to meet the needs of every segment of the industry, for manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website. For more information, visit


Emily Desjardins