Server Forum Taiwan

Friday, May 17 • Hsinchu

 Program Moderator:  William Shen, Winbond
9:30-9:55AM

TSIA Welcome

Dr. Tzi-cker Chiueh, General Director of Information and Communications Research Labs of ITRI and Chairman of IC Design Committee of TSIA

9:55-10:00AM

JEDEC Welcome

Mian Quddus, JEDEC Board of Directors

Morning Session

10:00-10:30AM
Keynote

Server Memory Architecture to Meet the Demands of the Next Decade

Keynote Presenter: Stuart Berke, Dell

The mainstream server memory subsystem is under unprecedented pressure to deliver the memory BW needed by next generation Processors and IO and Fabric links, support emerging Storage Class and Persistent Memories, and Improve Reliability, Availability, Serviceability, and Security.

This presentation will highlight key industry trends, explore looming and future challenges, and provide a peak at some of the architectural and ecosystem advances expected to be deployed in the decade ahead.
 

10:30-11:00AM
Keynote

DDR5 Technology Overview, Opportunities and Challenges

Keynote Presenter: Dr. Gang Zhao, Huawei

A high-level review of new features in the DDR5 DRAM devices and DIMM modules for server and data center applications, including market demands and challenges in various market segments and applications. A brief review of the new testing system and methodology is also included.

11:00-11:30AM
Keynote

At the forefront of DRAM technology for better Datacenter Services

Keynote Presenter: DS Kim, Samsung

These days, there are many types of services to help enjoy life such as SNS, Gaming, Education, Medical Autonomous vehicles, etc.

As the services keep evolving to deliver more and better user experiences, DRAM technology must also deliver better performance, higher density and more efficiency.

This keynote will introduce new DRAM products and describe the long-term view of DRAM technology.

11:30AM-12:00PM
Keynote
 

Server Memory in the age of the Cloud

Keynote Presenter: Desi Rhoden, Montage

The challenges and solutions for memory modules as the world migrates to the cloud. Maximizing performance, density, channel resources, and expanding memory types all while balancing low power and low cost demands from the solution providers.

12:00-1:00PMLunch Break

Afternoon Session

1:00-1:30PM

Getting Ready for DDR5

Presenter: Charles Chang, Intel

In this talk we will discuss getting industry ready for DDR5. This includes DDR5 value prop, DDR5 component and module overview, JEDEC spec status, how we are getting ready, test and validation challenges, summary & call to action.

1:30-2:00PM

NVDIMM-P for New Memory Ecosystem

 Presenter: Benjamin Lim, Samsung

Description

Along with the Big Data era, many people in the server industry are talking about new memory and ecosystems. This presentation introduces several industrial approaches for adopting new memory and describes the basic concepts of the NVDIMM-P protocol that can use various new memory media in existing DIMM sockets.

2:00-2:30PM

Gearing up to DDR5 for TCO Savings in Data Centers

Presenter: Sam Byungsoo Kim, SK hynix

In this presentation, server system trends, market trends focused on DDR5, key changes and value propositions of DDR5 will be highlighted, alongside few previous SK hynix public releases related to DDR5.

2:30-2:45PMBreak
2:45-3:15PM

DDR5: Mainstream Memory That Maximizes Effective Bandwidth

Presenter: Ryan Baxter, Micron

The “data economy” is driving demand for higher-bandwidth memory due to increasing CPU core counts, frequency, and IPC. The explosion in compute capability magnifies the pressure on memory and storage, requiring more bits and higher bandwidth. Tiered solutions of memory and storage are the reality of the future. This presentation explains how DDR5 will make a difference for compute-intensive applications and provides examples of how DDR5 improves performance on specific workloads and enables real-world bandwidth improvements.

3:15-3:45PM

DDR5 DIMM Architecture & Eco System Overview

Presenter: Sam Patel, IDT

The complexity of DDR5 server memory sub-system has become ever so complex to meet the performance, capacity and power requirements for future generation of SoCs. This presentation will address all components on the DDR5 DIMM except for DRAM and how each component plays a role in delivering solution to future generation of SoCs and platforms. An overview of new approach to deliver power to the memory; to deliver reliable & high performance system management bus communication, DIMM temperature control and preview of security challenges and possible solution space is addressed in this presentation.

3:45-4:15PM

How Measurement Science informs the DDR5 specification

Presenter: Perry Keller, Keysight

Over time, as DDR speeds have increased, the fundamental approach used to move data has had to change. Traditional High Speed Digital timing and noise with min/typ/max specifications gave way in DDR4 to High Speed Serial approaches based on eye masks with random and deterministic noise and jitter specifications. DDR5 must go a step further to deal with closed eyes using tunable equalization with the specification describing limits on the impulse response of the Tx/bus/Rx channel. At each point the need to characterize and measure what’s defined in the spec has made Measurement Science and DFT increasingly important in defining the DDR spec. This session will focus on the Measurement Science behind the DDR5 specification.

4:15-4:45PM

New Characterization Techniques for DDR5 Memory Generation and Beyond

Presenter: David Yang, Tektronix

With the 5G standard knocking on the door, datacenters will need to access a large amount of data at faster speeds and lower the power consumption at the same time. DDR5 provides double the bandwidth and density over DDR4 and delivers improved channel efficiency. Join Tektronix as we provide an update on the latest characterization and debug techniques to enable analysis of the highest DDR5 speed grades.

Program, topics and speakers subject to change without notice.