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Displaying 1 - 8 of 8 documents. Show 5 results per page.

Title	Document #	Date
CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINE Status: Reaffirmed February 2023	JP002	Mar 2006
This document will provide insight into the theory behind tin whisker formation as it is known today and, based on this knowledge, potential mitigation practices that may delay the onset of, or prevent tin whisker formation. The potential effectiveness of various mitigation practices will also be briefly discussed. References behind each of the theories and mitigation practices are provided. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
MEASURING WHISKER GROWTH ON TIN AND TIN ALLOY SURFACE FINISHES Status: Reaffirmed May 2014, September 2019	JESD22-A121A	Jul 2008
The predominant terminal finishes on electronic components have been Sn-Pb alloys. As the industry moves toward Pb-free components and assembly processes, the predominant terminal finish materials will be pure Sn and alloys of Sn, including Sn-Bi and Sn-Ag Pure Sn and Sn-based alloy electrodeposits and solder-dipped finishes may grow tin whiskers, which could electrically short across component terminals or break off the component and degrade the performance of electrical or mechanical parts. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
ENVIRONMENTAL ACCEPTANCE REQUIREMENTS FOR TIN WHISKER SUSCEPTIBILITY OF TIN AND TIN ALLOY SURFACE FINISHED Status: Reaffirmed May 2014, January 2020	JESD201A	Sep 2008
The methodology described in this document is applicable for environmental acceptance testing of tin based surface finishes and mitigation practices for tin whiskers. This methodology may not be sufficient for applications with special requirements, (i.e., military, aerospace, etc.). Additional requirements may be specified in the appropriate requirements (procurement) documentation. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES	JEP122H	Sep 2016
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. Committee(s): JC-14.2 Available for purchase: $163.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONIC HARDWARE	JEP70C	Oct 2013
This document gathers and organizes common standards and publications relating to quality processes and methods relating to the solid-state, microelectronics, and associated industries. This is intended to facilitate access to the applicable documents when working with electronic hardware. This will have a positive effect on quality and reliability as users gain more access to proper methods in designing, producing, and testing parts. Committee(s): JC-14.4 Free download. Registration or login required.
Information Requirements for the Qualification of Solid State Devices	JESD69D	Jun 2024
This standard defines the requirements for the device qualification package, which the supplier provides to the customer. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES	JEP143D	Jan 2019
The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
DICTIONARY OF TERMS FOR SOLID-STATE TECHNOLOGY, 7th Edition	JESD88F	Feb 2018
This reference for technical writers and educators, manufacturers, and buyers and users of discrete solid state devices is now available. It should aid the technical committees of JEDEC in the avoidance of multiple definitions and reduce the proliferation of redundant definitions. The long-term goal is to include definitions from all JEDEC publications and standards. Each of the approximately two thousand entries is referenced to its source publication, and an annex listing the names of the source publications and their releases dates is included. All entries were reviewed for punctuation, grammar, and clarity, as well as accuracy, and reworded if such was considered warranted. The purpose of this dictionary is to promote the uniform use of terms, definitions, abbreviations, and symbols throughout the solid state industry Committee(s): JC-10 Free download. Registration or login required.