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Title Document # Date

SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD

 JESD218B.03 Aug 2024

Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser.  Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32

Committee(s): JC-64.8

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Automotive Solid State Drive (SSD) Device Standard

Release Number: 1.0 		JESD312 Nov 2022

This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features for a solid state drive (SSD) targeted primarily at automotive applications.

Committee(s): JC-64, JC-64.8

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ENCLOSURE FORM FACTOR FOR SSD DEVICES, VERSION 1.0

 JESD253.01 Aug 2021

This document specifies the enclosure form factor which can be used with various type of SSD devices: outline of the top and bottom enclosure, three screw holes to mount the enclosure on the system, and two clamping holes in the top enclosure to lock to the connector. Item 318.06. This is a minor editorial revision detailed in Annex D.

Committee(s): JC-64.8

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SOLID-STATE DRIVE (SSD) ENDURANCE WORKLOADS

 JESD219A.01 Jun 2022

Terminology update, see Annex. This standard defines workloads for the endurance rating and endurance verification of SSD application classes. These workloads shall be used in conjunction with the Solid State Drive (SSD) Requirements and Endurance Test Method standard, JESD218. Also see JESD219A_MT and JESD219A_TT for the supporting trace files.

Committee(s): JC-64, JC-64.8

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Registration - Enclosure Form Factor for Automotive SSD Connector, Cable Mount

 SO-029A Jan 2022

Designator: PBXC-K4_D#p##-MR36p05x14p5Z10p25-HS

 

Item: 11.14-210, Access STP Files for SO-029A

Cross Reference: MO-348

Committee(s): JC-11.14

JEP95 Registrations Main Page

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Registration - mSATA SSD Assembly. DIM.

MO-300C Mar 2015

Item 11.14-175

Committee(s): JC-11, JC-11.14

JEP95 Registrations Main Page

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MASTER TRACE FOR 128 GB SSD

 JESD219A_MT Jul 2012

The Master Trace file is a supporting file for implementation of the endurance verification client workload and is used in conjunction with JESD219A. This Master Trace represents actual SSD activity over a period of seven months. It is used as the client workload for endurance verification per JESD218 of SSDs with user capacities greater than or equal to 64 GB. This Master Trace may be used as the Test Trace for endurance verification of a 128 GB to 256 GB SSD with its existing LBA range. This Master trace may be compressed or expanded to be used with capacities less than 128 GB or greater than 256 GB, respectively. The compressed or expanded Test Trace shall be applicable to SSDs with a maximum LBA that is less than or equal to 2x the maximum LBA of the Test Trace (e.g., a user capacity from 1x to 2x of the Test Trace capacity supported).

Committee(s): JC-64.8

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SPECIALITY DDR2-1066 SDRAM

 JESD208 Nov 2007

This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices.

Committee(s): JC-42.3

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DDR2 SDRAM STANDARD

 JESD79-2F Nov 2009

This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01

Committee(s): JC-42, JC-42.3

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TEST TRACE FOR 64 GB - 128 GB SSD

 JESD219A_TT Jul 2012

The Test Trace file is a supporting file for implementation of the endurance verification client workload and is used in conjunction with JESD219A. This Test Trace is derived from the 128 GB Master Trace using the compression method described in JESD219 to enable testing on SSDs with a capacity range of 64 GB to 128 GB. All characteristics of this Test Trace are identical to the Master Trace except that the maximum LBA represents an SSD user capacity of 64 GB.

Committee(s): JC-64.8

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DDR3 Unbuffered Mini-DIMM, Annex B

 PRN11-NM2 Jun 2011

Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release JESD21C. Item 2201.10

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

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MCP and Discrete e•MMC, e•2MMC, and UFS

Release Number: 33 		MCP3.12.1-1 Jun 2024

Item 142.12

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

 

Committee(s): JC-64.2

JESD21-C Solid State Memory Documents Main Page

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Nibble Wide SDRAM

 SDRAM3.11.2 Jan 2004

Release No.13

Committee(s): JC-42, JC-42.3

JESD21-C Solid State Memory Documents Main Page

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Byte Wide SDRAM

 SDRAM3.11.3 Jan 2004

Release No.13

Committee(s): JC-42, JC-42.3

JESD21-C Solid State Memory Documents Main Page

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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification

 MODULE4.20.13 May 2021

Release 31.  Item 2167.05

This revision contains terminology updates only.

Committee(s): JC-45, JC-45.2, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.

MODULE4.20.10 Jan 2010

Release No. 19A.  Items 2133.37, 2191.00, 2191.02, 2129.12, 2113.33.

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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UNIVERSAL FLASH STORAGE (UFS) UNIFIED MEMORY EXTENSION, Version 1.1

 JESD220-1A Mar 2016

This UFS Unified Memory Support Extension standard is an extension to the UFS standard, JESD220, This standard defines a managed storage device. UFS devices are designed to offer a high performance with low power consumption. The UFS device contains features that support both high throughput for large data transfers and performance for small random data accesses. This standard describes the requirements to implement unified memory functionality in an UFS device. Unified Memory Support is not mandatory but optional. Item 133.11

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-64.1

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Word Wide SDRAM.

 SDRAM3.11.4 Feb 2008

Release No. 17. Item 1749.01

Committee(s): JC-42.3

JESD21-C Solid State Memory Documents Main Page

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PC2-4200/PC2-3200 DDR2 Registered Mini-DIMM Design Specification Revision 2.0

 MODULE4.20.14 Dec 2006

Release No. 16. Item 2105.00

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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FBDIMM STANDARD: DDR2 SDRAM FULLY BUFFERED DIMM (FBDIMM) DESIGN STANDARD

 JESD205 Mar 2007

This standard defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/PC2-6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).These SDRAM FB-DIMMs are intended for use as main memory when installed in systems such as servers and workstations. PC2-4200/PC2-5300/PC2-6400 refers to the DIMM naming convention in which PC2-4200/PC2-5300/PC2-6400 indicates a 240-pin DDR2 DIMM running at 266/333/400 MHz DRAM clock speed and offering 4266/5333/6400 MB/s bandwidth.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-45, JC-45.4

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