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Title	Document #	Date
OVERVIEW OF METHODOLOGIES FOR THE THERMAL MEASUREMENT OF SINGLE- AND MULTI-CHIP, SINGLE- AND MULTI-PN-JUNCTION LIGHT-EMITTING DIODES (LEDS)	JESD51-50A	Nov 2022
This document provides an overview of the methodology necessary for making meaningful thermal measurements on high-power light-emitting diodes (LEDs) built on single or multiple chips with one or more pn-junctions per chip. The actual methodology components are contained in separate detailed documents. Committee(s): JC-15 Free download. Registration or login required.
SPD Annex J: Serial Presence Detect for DDR2 SDRAM	SPD4.1.2.10	Jan 2007
Release No. 17 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES:	JESD51- 7	Feb 1999
This fixturing further defines the environment for thermal test of packaged microelectronic devices. Its function is to provide an alternate mounting surface for the analysis of heat flow in electronic components. The objective of the standard is to provide a high effective thermal conductivity mounting surface that can be compared equally against standard tests done in different laboratories with typical variations of less than or equal to 10%. Committee(s): JC-15.1 Free download. Registration or login required.
THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP)	JESD51-4A	Jul 2019
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations. Committee(s): JC-15 Free download. Registration or login required.
SPD Annex G, Serial Presence Detect for FBDIMM, Revision 1.1	SPD4.1.2.7	Jun 2006
Release No. 16A. Item 2003.02A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)- SUPERSEDED BY JESD51-4, September 1997. Status: ElevatedSeptember 1997	JEP129	Feb 1997
Committee(s): JC-15.1 Free download. Registration or login required.
INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD - ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE):	JESD51- 1	Dec 1995
The purpose of this test method is to define a standard Electrical Test Method (ETM) that can be used to determine the thermal characteristics of single integrated circuit devices housed in some form of electrical package. This method will provide a basis for comparison of different devices housed in the same electronic package or similar devices housed in different electronic packages. Committee(s): JC-15.1 Free download. Registration or login required.
APPLICATION THERMAL DERATING METHODOLOGIES:	JEP149.01	Jan 2021
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
COMPACT THERMAL MODEL OVERVIEW	JESD15-1.01	Mar 2023
Terminology update. This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
THERMAL MODELING OVERVIEW	JESD15	Oct 2008
This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology components are contained in separate detailed documents. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES:	JESD51- 3	Aug 1996
This standard describes design requirements for a single layer, leaded surface mount integrated circuit package thermal test board. The standard describes board material and geometry requirements, minimum trace lenghts, trace thickness, and routing considerations. Application includes still air and moving air thermal tests. Committee(s): JC-15.1 Free download. Registration or login required.
METHODOLOGY FOR THE THERMAL MEASUREMENT OF COMPONENT PACKAGES (SINGLE SEMICONDUCTOR DEVICE)	JESD51	Dec 1995
This standard and its subsequent addendum's, provides a standard for thermal measurement that, if followed fully, will provide correct and meaningful data that will allow for determination of junction temperature for specific conditions. The data can be used for package design evaluation, device characterization and reliability predictions. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
MECHANICAL SHOCK – DEVICE AND SUBASSEMBLY	JESD22-B110B.01	Jun 2019
Device and Subassembly Mechanical Shock Test Method is intended to evaluate devices in the free state and assembled to printed wiring boards for use in electrical equipment. The method is intended to determine the compatibility of devices and subassemblies to withstand moderately severe shocks. The use of subassemblies is a means to test devices in usage conditions as assembled to printed wiring boards. Mechanical Shock due to suddenly applied forces, or abrupt change in motion produced by handling, transportation or field operation may disturb operating characteristics, particularly if the shock pulses are repetitive. This is a destructive test intended for device qualification.This document also replaces JESD22-B104. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600	JESD79-3-2	Oct 2011
The purpose of this addendum is to define the DDR3U specifications that supersede the DDR3 specifications in the JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 titles in JESD79-3 are to be interpreted as DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600, respectively, when applying towards DDR3U definition; unless specifically stated otherwise. Item 1769.01 Committee(s): JC-42.3 Free download. Registration or login required.
Part Model Supply Chain Guidelines for Electronic-Device Packages – XML Requirements	JEP30-S100A.02	Feb 2025
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14.4 Free download. Registration or login required.
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements	JEP181A	Nov 2023
This publication establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. Committee(s): JC-15 Free download. Registration or login required.
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS	JESD82-29A.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.3, JC-40.4 Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
DDR2 SDRAM STANDARD	JESD79-2F	Nov 2009
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
Graphics Double Data Rate (GDDR6) SGRAM Standard	JESD250D	May 2023
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required.

Standards & Documents Search

OVERVIEW OF METHODOLOGIES FOR THE THERMAL MEASUREMENT OF SINGLE- AND MULTI-CHIP, SINGLE- AND MULTI-PN-JUNCTION LIGHT-EMITTING DIODES (LEDS)

SPD Annex J: Serial Presence Detect for DDR2 SDRAM

HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES:

THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP)

SPD Annex G, Serial Presence Detect for FBDIMM, Revision 1.1

THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)- SUPERSEDED BY JESD51-4, September 1997.

INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD - ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE):

APPLICATION THERMAL DERATING METHODOLOGIES:

COMPACT THERMAL MODEL OVERVIEW

THERMAL MODELING OVERVIEW

LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES:

METHODOLOGY FOR THE THERMAL MEASUREMENT OF COMPONENT PACKAGES (SINGLE SEMICONDUCTOR DEVICE)

MECHANICAL SHOCK – DEVICE AND SUBASSEMBLY

Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600

Part Model Supply Chain Guidelines for Electronic-Device Packages – XML Requirements

ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements

DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

SPECIALITY DDR2-1066 SDRAM

DDR2 SDRAM STANDARD

Graphics Double Data Rate (GDDR6) SGRAM Standard

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