Global Standards for the Microelectronics Industry
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| Title | Document # | Date |
|---|---|---|
HIGH BANDWIDTH MEMORY (HBM) DRAM |
JESD235A | Nov 2015 |
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet. Item 1797.99F. Committee(s): JC-42.3 Free download. Registration or login required. |
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