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Displaying 1 - 12 of 12 documents. Show 5 | 10 results per page.

Title	Document #	Date
RECOMMENDED ESD-CDM TARGET LEVELS	JEP157A	Apr 2022
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS This is an editorial revision, details can be found in Annex F.	JEP162A.01	Jan 2021
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES	JEP143D	Jan 2019
The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
UNDERSTANDING ELECTRICAL OVERSTRESS - EOS	JEP174	Sep 2016
This purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper is to clarify what EOS really is and how it can be mitigated once it is properly comprehended. Committee(s): JC-14.3 Free download. Registration or login required.
UNIVERSAL FLASH STORAGE, UFS 2.2	JESD220C-2.2	Aug 2020
The purpose of this standard is definition of a UFS Universal Flash Storage electrical interface and a UFS memory device. This standard defines a unique UFS feature set and includes the feature set of eMMC standard as a subset. This standard replaces JESD220C, UFS 2.1, and introduces a feature called WriteBooster. Item 138.88. Committee(s): JC-64.1 Free download. Registration or login required.
SYSTEM LEVEL ESD PART 1: COMMON MISCONCEPTIONS AND RECOMMENDED BASIC APPROACHES Status: ReaffirmedJune 2016	JEP161	Jan 2011
This report is the first part of a two part document. Part I will primarily address hard failures characterized by physical damage to a system (failure category d as classified by IEC 61000-4-2). Soft failures, in which the system’s operation is upset without physical damage, are also critical and predominant in many cases. Committee(s): JC-14.3, JC-14 Free download. Registration or login required.
PART MODEL ELECTRICAL GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS	JEP30-E100	Apr 2018
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model. Committee(s): JC-11.2 Free download. Registration or login required.
Universal Flash Storage (UFS), Version 2.1 Status: Superseded August 2020	JESD220C-2.1	Mar 2016
This document has been superseded by JESD220C-2.2, August 2020, and is provided here for reference purposes only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. The architectural model is referencing the INCITS T10 (SCSI) SAM standard and the command protocol is based on INCITS T10 (SCSI) SPC and SBC standards. Item 133.00B Committee(s): JC-64.1 Free download. Registration or login required.
UNIVERSAL FLASH STORAGE (UFS), Version 3.0 Status: Superseded January 2020	JESD220D	Jan 2018
This document has been superseded by JESD220E, January 2020, however is available for reference only. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-64.1 Available for purchase: $355.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
UNIVERSAL FLASH STORAGE (UFS), Version 3.1	JESD220E	Jan 2020
This document replaces all past versions, however JESD220D, January (V 3.0), is available for reference only.The purpose of this standard is definition of an UFS Universal Flash Storage electrical interface and an UFS memory device. This standard defines a unique UFS feature set and includes the feature set of e·MMC Specification as a subset. This standard references also several other standard specifications by MIPI (M-PHY and UniPro Specifications) and INCITS T10 (SBC, SPC and SAM Standards) organizations. For more information about how to access and download the MIPI specifications related to UFS, visit: https://www.mipi.org/mipi-jedec/DocumentRequestWelcome. Item 135.99 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-64.1 Available for purchase: $355.00 Add to Cart Paying JEDEC Members may login for free access.
DICTIONARY OF TERMS FOR SOLID-STATE TECHNOLOGY, 7th Edition	JESD88F	Feb 2018
This reference for technical writers and educators, manufacturers, and buyers and users of discrete solid state devices is now available. It should aid the technical committees of JEDEC in the avoidance of multiple definitions and reduce the proliferation of redundant definitions. The long-term goal is to include definitions from all JEDEC publications and standards. Each of the approximately two thousand entries is referenced to its source publication, and an annex listing the names of the source publications and their releases dates is included. All entries were reviewed for punctuation, grammar, and clarity, as well as accuracy, and reworded if such was considered warranted. The purpose of this dictionary is to promote the uniform use of terms, definitions, abbreviations, and symbols throughout the solid state industry Committee(s): JC-10 Free download. Registration or login required.
RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION	JEP155B	Jul 2018
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. It will be shown through this document why realistic modifying of the ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different sections to give as many technical details as possible to support the purpose given in the abstract. In June 2009 the formulating committee approved the addition of the ESDA logo on the covers of this document. Please see Annex C for revision history. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.

Standards & Documents Search

RECOMMENDED ESD-CDM TARGET LEVELS

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES

UNDERSTANDING ELECTRICAL OVERSTRESS - EOS

UNIVERSAL FLASH STORAGE, UFS 2.2

SYSTEM LEVEL ESD PART 1: COMMON MISCONCEPTIONS AND RECOMMENDED BASIC APPROACHES

PART MODEL ELECTRICAL GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS

Universal Flash Storage (UFS), Version 2.1

UNIVERSAL FLASH STORAGE (UFS), Version 3.0

UNIVERSAL FLASH STORAGE (UFS), Version 3.1

DICTIONARY OF TERMS FOR SOLID-STATE TECHNOLOGY, 7th Edition

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION

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