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Title Document # Date

DDR5 SDRAM

Release Number: Version 1.2 		JESD79-5B Aug 2022

This standard defines the DDR5 SDRAM Specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Item 1848.99M.

Committee(s): JC-42.3B

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HIGH BANDWIDTH MEMORY (HBM3) DRAM

 JESD238A Jan 2023

The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR).

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-42, JC-42.2

Free download. Registration or required.

240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.

MODULE4.20.10 Jan 2010

Release No. 19A.  Items 2133.37, 2191.00, 2191.02, 2129.12, 2113.33.

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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FBDIMM STANDARD: DDR2 SDRAM FULLY BUFFERED DIMM (FBDIMM) DESIGN STANDARD

 JESD205 Mar 2007

This standard defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/PC2-6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).These SDRAM FB-DIMMs are intended for use as main memory when installed in systems such as servers and workstations. PC2-4200/PC2-5300/PC2-6400 refers to the DIMM naming convention in which PC2-4200/PC2-5300/PC2-6400 indicates a 240-pin DDR2 DIMM running at 266/333/400 MHz DRAM clock speed and offering 4266/5333/6400 MB/s bandwidth.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-45, JC-45.4

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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification

 MODULE4.20.13 May 2021

Release 31.  Item 2167.05This revision contains terminology updates only.

Committee(s): JC-45, JC-45.2, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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TS5111, TS5110 Serial Bus Thermal Sensor Device Standard

 JESD302-1.01 Apr 2022

This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS5111 and TS5110 refers to the device specified by this document. Item 401.01E. Minor editorial changes listed in Annex A.

Committee(s): JC-40.1

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240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification

 MODULE4.20.24 Apr 2014

Release No. 24. Item 2192.48A

Committee(s): JC-45.4

JESD21-C Solid State Memory Documents Main Page

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214-Pin DDR2 SDRAM Unbuffered MicroDIMM Design Specification

 MODULE4.20.12 Apr 2004

Release No. 14

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

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144-Pin EP2-2100 DDR2 SDRAM 32b S0DIMM Design Specification, Rev 1.0. Item 2043.09.

 MODULE4.20.16 Feb 2007

Release No. 16

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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144-Pin EP3-3200/EP3-4200/EP3-5300/EP3-6400 Unbuffered 32b-SO-DIMM Design Specification

 MODULE4.20.22 Feb 2012

Release 22

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

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PC2-4200/PC2-3200 DDR2 Registered Mini-DIMM Design Specification Revision 2.0

 MODULE4.20.14 Dec 2006

Release No. 16. Item 2105.00

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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DDR3 Unbuffered MicroDIMM Design Specification, 214-Pin PC3-12800. Item 2031.04

 MODULE4.20.17 Mar 2007

Release No. 17

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

MODULE4.20.20 Feb 2012

Release No. 22. Item 2082.94A

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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240-Pin, 72 bit-wide, PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

 MODULE4.20.23 Dec 2012

Release 22. Item 2082.94A

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

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LOW POWER DOUBLE DATA RATE 5 (LPDDR5)

 JESD209-5B Jun 2021

This document defines the LPDDR5 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5 device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3) and LPDDR4 (JESD209-4). Item  1854.99B.

Committee(s): JC-42, JC-42.6

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204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-S0-DIMM Design Specification

 MODULE4.20.21 Aug 2012

Release 22. Item 2189.17

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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JEDEC COMMITTEE SCOPE MANUAL

 JM18T Jun 2022

The JEDEC Board of Directors is responsible for establishing appropriate committees to conduct its standardization activities. These committees are assigned either service or product responsibilities. It is a primary function of each committee to propose JEDEC Standards and to formulate policies, procedures, formats, and other documents that are then submitted to the Board of Directors for action or approval. This publication identifies the service and product committees established by the Board of Directors and defines their scopes.

Committee(s): JC-COUN

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LRDIMM DDR3 MEMORY BUFFER (MB)

 JESD82-30.01 Jan 2023

Terminology update.

The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components.

Committee(s): JC-40, JC-40.4

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Fully Buffered DIMM Design for Test, Design for Validation (DFx)

 JESD82-28A.01 Mar 2023

Terminology update.  This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40, JC-40.5

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HIGH BANDWIDTH MEMORY (HBM) DRAM

 JESD235D Mar 2021

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L.

Committee(s): JC-42.3C

Available for purchase: $247.00 Add to Cart

Paying JEDEC Members may for free access.

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