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Annex N, R/C N, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2145.22

 MODULE4.20.20.N Sep 2012

Release No. 22. Item 2145.35

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex V, R/C V in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

 MODULE4.20.20.V May 2011

Release No. 21
Item 2145.27

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex W, R/C W, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.07

 MODULE4.20.20.W Aug 2009

Release No. 19

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Annex Y, R/C Y, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.06

 MODULE4.20.20.Y Aug 2009

Release No. 19

Committee(s): JC-45.1, JC-45

JESD21-C Solid State Memory Documents Main Page

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BYTE ADDRESSABLE ENERGY BACKED INTERFACE

 JESD245E Apr 2022

This standard specifies the host and device interface for a DDR4 NVDIMM-N, which is a DIMM that achieves non-volatility by copying SDRAM contents into non-volatile memory (NVM) when host power is lost using an Energy Source managed by either the module or the host. This standard is used in conjunction with JESD248. Item 2233.54G

Committee(s): JC-45.6

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DDR3 DIMM Label

 PRN09-NM4 Oct 2009

Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 2099.01b

Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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DDR3 DIMM Product Label

Release Number: 28 		DIMM-LABEL4.19.3 Dec 2018

This section covers DDR3 DIMM labels.

Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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DDR3 SDRAM STANDARD

 JESD79-3F Jul 2012

This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-42.3

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DDR3 Unbuffered MicroDIMM Design Specification, 214-Pin PC3-12800. Item 2031.04

 MODULE4.20.17 Mar 2007

Release No. 17

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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DDR3 Unbuffered Mini-DIMM, Annex A

 PRN11-NM1 Jun 2011

Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of JESD21C. Item 2207.11

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

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DDR3 Unbuffered Mini-DIMM, Annex B

 PRN11-NM2 Jun 2011

Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release JESD21C. Item 2201.10

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

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DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)

 JESD82-31A.01 Jan 2023

Terminology update.

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-40.4

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DDR4 SDRAM STANDARD

 JESD79-4D Jul 2021

This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H

Committee(s): JC-42.3C

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DDR5 SDRAM

Release Number: Version 1.31 		JESD79-5C.01 Jul 2024

Version 1.31

This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4).

Committee(s): JC-42, JC-42.3

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DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS

Release Number: Release 1.3 		JESD400-5C Sep 2024

This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels.

Committee(s): JC-45

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DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

 JESD82-29A.01 Jan 2023

Terminology update.
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications.

The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.3, JC-40.4

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FBDIMM: ARCHITECTURE AND PROTOCOL

 JESD206.01 Feb 2023

Terminology update. 
This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5).

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40

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LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X

 JESD209-5C Jul 2023

This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4).

Committee(s): JC-42, JC-42.6

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LOW POWER DOUBLE DATA RATE 2 (LPDDR2)

 JESD209-2F Jun 2013

This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01G.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-42.6

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LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)

 JESD209-3C Aug 2015

This document defines the LPDDR3 Standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices.

This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Committee Item no. 1798.11D.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-42.6

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