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Title	Document #	Date
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 5 Release Number: 29	SPD4.1.2.L-5	Aug 2019
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 5. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2276.05. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR3 DIMM Product Label Release Number: 28	DIMM-LABEL4.19.3	Dec 2018
This section covers DDR3 DIMM labels. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex M, Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules, Document Release 2 Release Number: 28	SPD4.1.2.M-2	Aug 2018
This annex describes the serial presence detect (SPD) values for all LPDDR modules covered in Document Release 2. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2254.02A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules, Release 1 Release Number: 25	SPD4.1.2.M-1	Nov 2015
Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1 Device Type Identifier: LP-DIMM Revision 1.0 This Annex describes the serial presence detect (SPD) values for all LPDDR modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in Section 2, with the exception of bytes 128~255 which are documented in separate sections, one for each family of module types. Further description of Byte 2 is found in Annex A of the SPD standard. Item 2254.01 Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 3 Release Number: 25	SPD4.1.2.L-3	Sep 2015
This annex describes the serial presence detect (SPD) values for all DDR4 modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in section 1.1 with the exception of bytes 128~255 which are documented in separate annexes, one for each family of module types. Further description of Byte 2 is found in Annex A of the SPD standard. Item 2220.01F. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)	JESD209-3C	Aug 2015
This document defines the LPDDR3 Standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Committee Item no. 1798.11D. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Available for purchase: $208.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
WIDE I/O 2 (WideIO2)	JESD229-2	Aug 2014
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required.
204-Pin DDR3 SDRAM Unbuffered SODIMM Design Specification	MODULE4.20.18	May 2014
Release No. 24; Item 2114.44 Committee(s): JC-45, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification	MODULE4.20.24	Apr 2014
Release No. 24. Item 2192.48A Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex C, R/C C, in 240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification	MODULE4.20.24.C	Apr 2014
Release No. 24. Item 2192.54 Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex K, R/C K, in 240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification	MODULE4.20.24.K	Apr 2014
Release No. 24. Item 2192.68 Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex A, R/C A, in 240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification	MODULE4.20.24.A	Apr 2014
Release No. 24. Item 2192.58B Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules, Release 6	SPD4.1.2.11	Feb 2014
Release No. 24. Item 2065.47A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 2 Release Number: 23A	SPD4.1.2.L-2	Jan 2014
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 2. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. (This release is editorial changes only). Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 3 to JESD79-3, 3D STACKED SDRAM	JESD79-3-3	Dec 2013
This addendum to JESD79-3 defines the 3DS DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for compliant 8Gbit through 64Gbit x4 and x8 3DS DDR3 SDRAM devices. This document was created based on the E revision of the DDR standard (JESD79). Each aspect of the changes for 3DS DDR3 SDRAM operation was considered. Committee(s): JC-42.3 Free download. Registration or login required.
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 1 Release Number: 23	SPD4.1.2.L-1	Nov 2013
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 1. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01 Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-RDIMM ANNEX D (x8 2R, Planar)	PRN13-NM3	Oct 2013
Item No. 2207.14 (JC-45.1-12-284, JCB-12-63) Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-UDIMM RC F0(x8 2R, STACKED)	PRN13-NM1	Oct 2013
Item No. 2229.01 (JC-45.3-11-523, JCB-11-102) Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144-Pin EP3-3200/EP3-4200/EP3-5300/EP3-6400 Unbuffered 32b-SO-DIMM Design Specification	MODULE4.20.22.D	Aug 2013
Release 22. Item 2227.09A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-SODIMM Design Specification	MODULE4.20.21.D	Aug 2013
Release No. 23 Item 2114.29A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Standards & Documents Search

SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 5

DDR3 DIMM Product Label

Annex M, Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules, Document Release 2

Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules, Release 1

SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 3

LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)

WIDE I/O 2 (WideIO2)

204-Pin DDR3 SDRAM Unbuffered SODIMM Design Specification

240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification

Annex C, R/C C, in 240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification

Annex K, R/C K, in 240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification

Annex A, R/C A, in 240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification

SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules, Release 6

SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 2

Addendum No. 3 to JESD79-3, 3D STACKED SDRAM

SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 1

PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-RDIMM ANNEX D (x8 2R, Planar)

PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-UDIMM RC F0(x8 2R, STACKED)

144-Pin EP3-3200/EP3-4200/EP3-5300/EP3-6400 Unbuffered 32b-SO-DIMM Design Specification

204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-SODIMM Design Specification

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