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This UFS Unified Memory Support Extension standard is an extension to the UFS standard, JESD220, This standard defines a managed storage device. UFS devices are designed to offer a high performance with low power consumption. The UFS device contains features that support both high throughput for large data transfers and performance for small random data accesses. This standard describes the requirements to implement unified memory functionality in an UFS device. Unified Memory Support is not mandatory but optional. Item 133.11

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Committee(s): JC-64.1

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This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. Item 205.06

This document replaces all past versions, however JESD223C, March 2016 (V 2.1), is available for reference only.

Committee(s): JC-64.1

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A revised reference for technical writers and educators, manufacturers, buyers and users of microprocessors, microcomputers, mircocontrollers, memory ICs, and other complex devices. The terms and their definitions in this standard have been updated and are in general agreement with the latest publications of the IEEE and the IEC. The companion standard for other integrated circuits is JESD99A. Also included is a system for generating symbols for time intervals found in complex sequential circuits, including memories. JESD100B.01 is the first minor revision of JESD100-B, December 1999. Annex A briefly shows entries that have changed.

Committee(s): JC-10

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This document has been superseded by JESD223D, January 2018, however is available for reference only.

Committee(s): JC-64.1

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This reference for technical writers and educators, manufacturers, and buyers and users of discrete solid state devices is now available. It should aid the technical committees of JEDEC in the avoidance of multiple definitions and reduce the proliferation of redundant definitions. The long-term goal is to include definitions from all JEDEC publications and standards. Each of the approximately two thousand entries is referenced to its source publication, and an annex listing the names of the source publications and their releases dates is included. All entries were reviewed for punctuation, grammar, and clarity, as well as accuracy, and reworded if such was considered warranted. The purpose of this dictionary is to promote the uniform use of terms, definitions, abbreviations, and symbols throughout the solid state industry

Committee(s): JC-10

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The purpose of this standard is the definition of the MMC/e•MMC Electrical Interface, its environment and handling. It provides guidelines for systems designers. The standard also defines a tool box (a set of macro functions and algorithms) that contributes to reducing design-in costs.

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Committee(s): JC-64.1

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This document is a complete specification for embedded memory devices and removable memory cards using the MMC interface version 4.3. New features developed through the Electrical Joint Task Group include: Sleep mode, Boot mode and Reliable Write.

Committee(s): JC-64, JC-64.2

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The purpose of the specification is the definition of the e•MMC, its environment and handling. It provides guidelines for systems designers. The specification also defines a tool box (a set of macro functions and algorithms) that contributes to reducing design-in costs.

Committee(s): JC-64.1, JC-64

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This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc.

Committee(s): JC-14.2

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