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Title Document # Date

DDR5 SDRAM

Release Number: Version 1.31 		JESD79-5C.01 Jul 2024

Version 1.31

This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4).

Committee(s): JC-42, JC-42.3

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DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS

Release Number: Release 1.3 		JESD400-5C Sep 2024

This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels.

Committee(s): JC-45

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LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X

 JESD209-5C Jul 2023

This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4).

Committee(s): JC-42, JC-42.6

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DDR5 DIMM Labels

 JESD401-5B.01 May 2024

This standard defines the labels that shall be applied to all DDR5 memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. A readable point size should be used, and the number can be printed in one or more rows on the label. Hyphens may be dropped when lines are split, or when font changes sufficiently.

Committee(s): JC-45

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DDR5 Registering Clock Driver Definition (DDR5RCD03)

Release Number: 1.00 		JESD82-513 Feb 2023

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD03 Device ID is DID = 0x0053.

Committee(s): JC-40, JC-40.5

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DDR5 Registering Clock Driver Definition (DDR5RCD04)

 JESD82-514.01 Jun 2024

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054.

Committee(s): JC-40, JC-40.4

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DDR5 Registering Clock Driver Definition (DDR5RCD02)

Release Number: Rev. 1.00 		JESD82-512 Feb 2023

This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052.

Committee(s): JC-40, JC-40.4

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DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD01)

 JESD82-511 Aug 2021

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD01 Device ID is DID = 0x0051.

Committee(s): JC-40.4

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Compression Attached Memory Module (CAMM2) Common Standard

 JESD318 Ver. 1.02 Nov 2023

This standard defines the electrical and mechanical requirements for Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LPDDR5/5X SDRAM CAMM2s).

Committee(s): JC-45

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LPDDR5/5X Serial Presence Detect (SPD) Contents

Release Number: 1.0 		JESD406-5 Jun 2024

This publication describes the serial presence detect (SPD) values for all LPDDR5/5X memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non-volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding.

Committee(s): JC-45

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DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1

 JESD82-521 Dec 2021

This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K

Committee(s): JC-40.4

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GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD

Release Number: C.01 - Terminology update 		JESD212C.01 Jan 2023

Terminology update. 
This document defines the Graphics Double Data Rate 5 (GDDR5) Synchronous Graphics Random Access Memory (SGRAM), including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC standard compatible 512 Mb through 8 Gb x32 GDDR5 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR5 SGRAM vendors providing JEDEC standard compatible devices. Some aspects of the GDDR5 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. Item 1733.70B

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Committee(s): JC-42.3C

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JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)

 JESD319 Sep 2024

This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC).

Committee(s): JC-40

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DDR5 262 Pin SODIMM Connector Performance Standard

 PS-006B Sep 2024

This standard defines the form, fit and function of SODIMM DDR5 connectors for modules supporting channels with transfer rates 6.4 GT/S and beyond. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide performance standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR5 connectors in client and server platforms. Item 14-226

Committee(s): JC-11, JC-11.14

JEP95 Registrations Main Page

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LPDDR5 CAMM2 Connector Performance Standard

 PS-007A Jul 2024

LPDDR5 CAMM2 Connector Performance Standard

Committee(s): JC-11, JC-11.14

JEP95 Registrations Main Page

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DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification

Release Number: Version 1.0 		JESD323 Jan 2024

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs). These DDR5 Clocked Unbuffered DIMMs (CUDIMMs) are intended for use as main memory when installed in Computers.

Committee(s): JC-45, JC-45.3

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DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification

Release Number: Version 1.0 		JESD324 Jan 2024

This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Clocked Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CSODIMMs). These DDR5 CSODIMMs are intended for use as main memory when installed in Computers, laptops and other systems.

Committee(s): JC-45, JC-45.3

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STANDARD - DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5

 PS-005B Oct 2022

This standard defines the form, fit and function of DDR5 connectors for U/R/LR modules supporting channels with transfer rates up to 6.4 GT/S. It contains mechanical, electrical and reliability requirements for connector mated to a module with nominal thickness of 1.27 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the DDR5 connectors in client and server platforms. Item 11.14-213S

Committee(s): JC-11.14

JEP95 Registrations Main Page

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DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard

Release Number: Version 1.1 		JESD308A Jan 2024

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers.

Committee(s): JC-45, JC-45.3

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GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD

 JESD232A.01 Mar 2023

Terminology update.  

This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package

Committee(s): JC-42.3, JC-42.3C

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