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This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 4. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01G. This is an editorial revision to the publication in January 2017.

Committee(s): JC-45

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This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 6. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01H.

Committee(s): JC-45

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This standard defines the Low Power Double Data Rate interface for Non-Volatile Memory (LPDDR4XNVM) Standard. This standard describes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements

for a JEDEC compliant 16 bit single channel LPDDR4X-NVM device. LPDDR4X-NVM density ranges from 128Mb through 32Gb.

Committee(s): JC-42, JC-42.6

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This annex describes the serial presence detect (SPD) values for all DDR4 modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in section 1.1 with the exception of bytes 128~255 which are documented in separate annexes, one for each family of module types. Further description of Byte 2 is found in Annex A of the SPD standard. Item 2220.01F.

Committee(s): JC-45

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This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 1. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01

Committee(s): JC-45

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This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G

Committee(s): JC-42.3C

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This document defines the electrical and mechanical requirements for 260 pin, 1.2 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops and other systems. This document also contains the DDR4 DIMM Label, Ranks Definition. Item 2224.13A

Committee(s): JC-45.3

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Terminology update.

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-40.4

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Item 1600.41, Terminology Update  

This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics Random

Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices.

Committee(s): JC-42.3

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