Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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144-Pin EP3-3200/EP3-4200/EP3-5300/EP3-6400 Unbuffered 32b-SO-DIMM Design Specification |
MODULE4.20.22.B | Aug 2013 |
Release 23. Item 2227.13 Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144-Pin EP2-2100 DDR2 SDRAM 32b S0DIMM Design Specification, Rev 1.0. Item 2043.09. |
MODULE4.20.16 | Feb 2007 |
Release No. 16 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144 Pin, PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification |
MODULE4.20.3 | Oct 2003 |
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144 Pin SGRAM/SDRAM SO-DIMM Family |
MODULE4.5.8 | Oct 2000 |
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144 Pin SDRAM SO-DIMM |
MODULE4.5.6 | Mar 1999 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144 Pin DRAM SO-DIMM |
MODULE4.5.5 | Mar 1999 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144 Pin DDR SGRAM SO-DIMM |
MODULE4.5.9 | Mar 1999 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM |
MODULE4.5.13 | Oct 2000 |
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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112 Pin MPDRAM DIMM |
MODULE4.4.6 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification |
MODULE4.20.9 | Nov 2004 |
Release No. 14 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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100 Pin DRAM, SDRAM, and ROM DIMM |
MODULE4.4.8 | Dec 1997 |
Release No. 8 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE |
JESD8-31 | Mar 2018 |
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.8 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.8 V. Committee(s): JC-16 Free download. Registration or login required. |
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1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE |
JESD8-26 | Sep 2011 |
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices. Committee(s): JC-16 Free download. Registration or login required. |
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1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS: |
JESD8-12A.01 | Sep 2007 |
This standard defines power supply voltage ranges, dc interface and switching parameters for a high speed, low voltage family of nonterminated digital circuits driving/driven by parts of the same family, or mixed families which comply with the input receiver specifications. The specifications in this standard represent a minimum set of interface specifications for CMOS compatible circuits. Committee(s): JC-16 Free download. Registration or login required. |
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1.05 V CMOS |
JESD8-34 | Apr 2020 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01 Committee(s): JC-16 Free download. Registration or login required. |
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1.0 V +/- 0.1 V (NORMAL RANGE) AND 0.7 V - 1.1 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS: |
JESD8-14A.01 | Sep 2007 |
This new standard provides specifications that will be used by several companies in new 1.0 V products designed in 0.10-0.12 um CMOS technologies, and in components that interface with them. This standard defines power supply voltage ranges, dc interface and switching parameters for a high speed, low voltage family of nonterminated digital circuits driving/driven by parts of the same family, or mixed families which comply with the input receiver specifications. The specifications in this standard represent a minimum set of interface specifications for CMOS compatible circuits. This version is a minor editorial revision as noted in Annex A. Committee(s): JC-16 Free download. Registration or login required. |
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0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06) |
JESD8-29 | Dec 2016 |
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits with 0.6V supply. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 180.24. Committee(s): JC-16 Free download. Registration or login required. |
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0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05) |
JESD8-33 | Jun 2019 |
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03 Committee(s): JC-16 Free download. Registration or login required. |
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Temperature Range and Measurement Standards for Components and Modules |
JESD402-1B | Sep 2024 |
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Committee(s): JC-42 Free download. Registration or login required. |
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REPLAY PROTECTED MONOTONIC COUNTER (RPMC) FOR SERIAL FLASH DEVICES |
JESD260 | Apr 2021 |
This document provides the requirements for an additional block called as Replay Protection Monotonic Counter. (RPMC) Replay Protection provides a building block towards providing additional security. This block requires modifications in both a Serial Flash device and Serial Flash Controller. The standard defines new commands for Replay Protected Monotonic Counter operations. A device that supports RPMC can support these new commands as defined in this standard. Committee(s): JC-42.4 Free download. Registration or login required. |