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Title	Document #	Date
Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package	MO-340A	Oct 2019
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04 Item: 11.11-974, Access STP Files for MO-340A Cross Reference: DR4.8, DR4.16, DR4.20 Patents(): Nexperia BV: 8809121B2 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package	MO-341A	Oct 2019
Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1 Item: 11.11-959 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE NOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded.	JEP106BA	Oct 2019
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS	JEP162A	Sep 2019
JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package	MO-338A	Sep 2019
Item 11.11-973, Access STP Files for MO-338A Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Bottom Flatpack 28 Terminal Package	MO-339A	Sep 2019
Item 11-11.975, STP File for MO-339A Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
DESCRIPTIVE DESIGNATION SYSTEM FOR ELECTRONIC-DEVICE PACKAGES	JESD30I	Aug 2019
This standard establishes requirements for the generation of electronic-device package designators for the JEDEC Solid State Technology Association. The requirements herein are intended to ensure that such designators are presented in as uniform a manner as practicable. Item 11.2-962. Committee(s): JC-11.2 Free download. Registration or login required.
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 5 Release Number: 29	SPD4.1.2.L-5	Aug 2019
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 5. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2276.05. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex L, Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 4 Release Number: 27A	SPD4.1.2.L-4	Aug 2019
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 4. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01G. This is an editorial revision to the publication in January 2017. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification Release Number: 29	MODULE4.20.25	Aug 2019
This document defines the electrical and mechanical requirements for 260 pin, 1.2 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops and other systems. This document also contains the DDR4 DIMM Label, Ranks Definition. Item 2224.13A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification Release Number: 29	MODULE4.20.26	Aug 2019
This specification defines the electrical and mechanical requirements for the 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs are intended for use as main memory when installed in PCs. Item 2241.13A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)	JESD216D.01	Aug 2019
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.15 and 1775.18. Committee(s): JC-42.4 Free download. Registration or login required.
DDR4 DIMM Product Label, Hybrid, Pre-Production, DDR4E Release Number: 29	DIMM-LABEL4.19.4	Aug 2019
This section covers DDR4 and DDR4E in both DRAM-only module types and Hybrid module types, as well as pre-production modules of both types. Item 2224.13A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)	JESD82-31A	Aug 2019
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications. Any TBDs as of this document, are under discussion by the formulating committee. Item 314.08F. *If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required.
DDR4 DATA BUFFER DEFINITION (DDR4DB02)	JESD82-32A	Aug 2019
This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D *If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required.
DDR5 DIMM SMT 288 PIN SOCKET OUTLINE 0.85 MM PITCH SKT	SO-023B	Jul 2019
Item 11.14-196 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP)	JESD51-4A	Jul 2019
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations. Committee(s): JC-15 Free download. Registration or login required.
0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05)	JESD8-33	Jun 2019
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03 Committee(s): JC-16 Free download. Registration or login required.
POD125 - 1.25 V PSEUDO OPEN DRAIN I/O	JESD8-30A	Jun 2019
This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
NAND FLASH INTERFACE INTEROPERABILITY	JESD230D	Jun 2019
This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. Item 1765.00 Committee(s): JC-42.4 Free download. Registration or login required.

Standards & Documents Search

Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package

Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package

STANDARD MANUFACTURERS IDENTIFICATION CODE

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package

Registration - Plastic Bottom Flatpack 28 Terminal Package

DESCRIPTIVE DESIGNATION SYSTEM FOR ELECTRONIC-DEVICE PACKAGES

SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 5

SPD Annex L, Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 4

260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)

DDR4 DIMM Product Label, Hybrid, Pre-Production, DDR4E

DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)

DDR4 DATA BUFFER DEFINITION (DDR4DB02)

DDR5 DIMM SMT 288 PIN SOCKET OUTLINE 0.85 MM PITCH SKT

THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP)

0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05)

POD125 - 1.25 V PSEUDO OPEN DRAIN I/O

NAND FLASH INTERFACE INTEROPERABILITY

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