Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
JEDEC MODULE SIDEBAND BUS (SidebandBus) |
JESD403-1 | Oct 2020 |
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.37C. Committee(s): JC-45 Free download. Registration or login required. |
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JEDEC Manual of Organization and Procedure |
JM21T | Oct 2020 |
The mission of JEDEC is to serve the solid state industry by creating, publishing, and promoting global acceptance of standards, and by providing a forum for technical exchange on leading industry topics. This manual provides guidance for JEDEC members and staff to perform their functions correctly in the standardization process. Committee(s): JC-BOD Free download. Registration or login required. |
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ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements |
JEP181 | Sep 2020 |
This standard establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. The data is held in an XML format, conforming to an XML schema that this document describes. Get the XML Schema: JEP181_Schema_R1p0. Committee(s): JC-15 Free download. Registration or login required. |
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UNIVERSAL FLASH STORAGE, UFS 2.2 |
JESD220C-2.2 | Aug 2020 |
The purpose of this standard is definition of a UFS Universal Flash Storage electrical interface and a UFS memory device. This standard defines a unique UFS feature set and includes the feature set of eMMC standard as a subset. This standard replaces JESD220C, UFS 2.1, and introduces a feature called WriteBooster. Item 138.88. Committee(s): JC-64.1 Free download. Registration or login required. |
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REGISTRATION - Upper PoP, Plastic Bottom Grid Array Ball, 0.40 mm Pitch Rectangular Family Package |
MO-344A | Aug 2020 |
Designator: PBGA-B#[#]_I0p40... Cross Reference: DR4.18 Committee(s): JC-11 Free download. Registration or login required. |
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UFS Card Socket Performance Standard |
PS-004A | Jul 2020 |
For UFS Card 6 Gb/sItem 11.14-195S Committee(s): JC-11.14 Free download. Registration or login required. |
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BYTE ADDRESSABLE ENERGY BACKED INTERFACE |
JESD245D | Jul 2020 |
The purpose of this standard is definition of an energy backed byte addressable function on a nonvolatile dual in-line memory module (NVDIMM). This standard defines the feature set and commands implemented by the energy backed byte addressable function on the NVDIMM. This standard is used in conjunction with JESD248. Item 2233.54F * A minor editorial change has been made to the table under 8.1.3.2, on page 47 on 9/1/2020, from the original posted version 8/18/2020. If you downloaded prior to 9/1/2020, please discard and use the current version. Committee(s): JC-45.6 Free download. Registration or login required. |
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Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch, Rectangular Family Package |
MO-276O | Jul 2020 |
Designator: PBGA-B#[#]_I0p5... Cross Reference: DR4.5 Committee(s): JC-11.11 Free download. Registration or login required. |
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DDR5 SDRAM |
JESD79-5 | Jul 2020 |
This document defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8Gb through 32Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3 & LPDDR4 standards (JESD79, JESD79-2, JESD79-3 & JESD209-4). Item 1848.99G. Committee(s): JC-42.3B Available for purchase: $369.00 Add to Cart Paying JEDEC Members may login for free access. |
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TEMPERATURE GRADE AND MEASUREMENT SPECIFICATIONS FOR COMPONENTS AND MODULES |
JESD402-1 | Jul 2020 |
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Item 1855.01A Committee(s): JC-42 Free download. Registration or login required. |
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PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1 |
JESD301-1 | Jun 2020 |
Definition of PMIC5000, PMIC5010 Voltage Regulator Device for Memory Module Applications Committee(s): JC-40.1 Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BB | Jun 2020 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Free download. Registration or login required. |
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Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 30 |
MODULE4.20.26.E | Jun 2020 |
This specification defines the electrical and mechanical requirements for Raw Card E, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.17B. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 30 |
MODULE4.20.26.B | Jun 2020 |
This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.29A. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex G, Raw Card G, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 30 |
MODULE4.20.25.G | May 2020 |
This annex defines the electrical and mechanical requirements for Raw Card G, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item No. 2228.34C Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex E, R/C E, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 30 |
MODULE4.20.25.E | May 2020 |
This specification defines the electrical and mechanical requirements for Raw Card E, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.33C. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex C, R/C C, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 30 |
MODULE4.20.25.C | May 2020 |
This annex defines the electrical and mechanical requirements for Raw Card C, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.31B Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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1.05 V CMOS |
JESD8-34 | Apr 2020 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01 Committee(s): JC-16 Free download. Registration or login required. |
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PRECONDITIONING OF NONHERMETIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING |
JESD22-A113I | Apr 2020 |
This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow). Committee(s): JC-14.1 Free download. Registration or login required. |
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288 PIN DDR5 U/R/LR DIMM, 0.85 MM PITCH. |
MO-329B | Apr 2020 |
Designator: PDMA-N288-I0p85-R133p8x5p57Z31p8R2p55x0p6 Patents(): Micron: 7,547,213. Committee(s): JC-11.14 Free download. Registration or login required. |
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