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Designator: N/A
Item: 11.2-991, Access STP Files for CO-036A
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Committee(s): JC-11.2

JEP95 Registrations Main Page

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Item 142.01, 142.02.This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. 

Committee(s): JC-64.2

JESD21-C Solid State Memory Documents Main Page

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RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01.

Committee(s): JC-42

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This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A.

Committee(s): JC-42.6

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This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.  The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such  as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Item 1836.99E.

Committee(s): JC-42.3C

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This document specifies the enclosure form factor which can be used with various type of SSD devices: outline of the top and bottom enclosure, three screw holes to mount the enclosure on the system, and two clamping holes in the top enclosure to lock to the connector. Item 318.06.

Committee(s): JC-64.8

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This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis.

Committee(s): JC-70.1

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This version is a minor editorial adding Annex B that was left out of the original publication October 2020.An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory.  A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K.

Committee(s): JC-45.6

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This standard identifies the best commercial practices for mitigating and/or avoiding counterfeit products by all manufacturers of electronic parts including, but not limited to original component manufacturers (OCMs), authorized aftermarket manufacturers, and other companies that manufacture electronic parts under their own logo, name, or trademark. The types of product this standard applies to is limited to monolithic microcircuits, hybrid microcircuits and discrete semiconductor products.

Committee(s): JC-13

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