Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
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ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS |
JEP178 | Apr 2021 |
This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries. Committee(s): JC-14.3 Free download. Registration or login required. |
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FLIP CHIP TENSILE PULL |
JESD22-B109C | Mar 2021 |
The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test. Committee(s): JC-14.1 Free download. Registration or login required. |
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Registration - Shipping and Handling Tray for DDR5 DIMM, 50 pcs |
CO-036A | Mar 2021 |
Designator: N/A Committee(s): JC-11.2 Free download. Registration or login required. |
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Registration - 39 Pin Removable Memory, 1.00 mm Pitch Microelectronic Assembly |
MO-347A | Mar 2021 |
Designator: PBMA-N32[39]_Ip0-R14p1x18p1Z1p65-R0p71x1p1 Patents(): Kioxia: 1705380 Committee(s): JC-11.11 Free download. Registration or login required. |
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Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFSRelease Number: 31 |
MCP3.12.1 | Mar 2021 |
Item 142.01, 142.02.This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SYSTEM LEVEL ROWHAMMER MITIGATION |
JEP301-1 | Mar 2021 |
A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02. Committee(s): JC-42 Free download. Registration or login required. |
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NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION |
JEP300-1 | Mar 2021 |
RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01. Committee(s): JC-42 Free download. Registration or login required. |
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HIGH BANDWIDTH MEMORY (HBM) DRAM |
JESD235D | Mar 2021 |
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L. Committee(s): JC-42.3C Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
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ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X) |
JESD209-4-1A | Feb 2021 |
This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A. Committee(s): JC-42.6 Available for purchase: $106.00 Add to Cart Paying JEDEC Members may login for free access. |
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Addendum No. 1 to JESD79-4, 3D STACKED DRAM |
JESD79-4-1B | Feb 2021 |
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G Committee(s): JC-42.3C Free download. Registration or login required. |
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GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD |
JESD250C | Feb 2021 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Item 1836.99E. Committee(s): JC-42.3C Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BC | Feb 2021 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Free download. Registration or login required. |
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ENCLOSURE FORM FACTOR FOR SSD DEVICES, VERSION 1.0 |
JESD253 | Feb 2021 |
This document specifies the enclosure form factor which can be used with various type of SSD devices: outline of the top and bottom enclosure, three screw holes to mount the enclosure on the system, and two clamping holes in the top enclosure to lock to the connector. Item 318.06. Committee(s): JC-64.8 Free download. Registration or login required. |
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Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick |
MO-193G | Feb 2021 |
Designator: PDSO-G#_I0P##-##... Item 11.11-990 Committee(s): JC-11.11 Free download. Registration or login required. |
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Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs |
JEP183 | Jan 2021 |
This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. Committee(s): JC-70.1 Free download. Registration or login required. |
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DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5 |
PS-005A | Jan 2021 |
Committee(s): JC-11.14 Free download. Registration or login required. |
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DDR4 NVDIMM-P BUS PROTOCOL |
JESD304-4.01 | Jan 2021 |
This version is a minor editorial adding Annex B that was left out of the original publication October 2020.An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory. A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K. Committee(s): JC-45.6 Free download. Registration or login required. |
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GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES |
JEP180.01 | Jan 2021 |
This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches. Committee(s): JC-70.1 Free download. Registration or login required. |
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COUNTERFEIT ELECTRONIC PARTS: NON-PROLIFERATION FOR MANUFACTURERS |
JESD243A | Jan 2021 |
This standard identifies the best commercial practices for mitigating and/or avoiding counterfeit products by all manufacturers of electronic parts including, but not limited to original component manufacturers (OCMs), authorized aftermarket manufacturers, and other companies that manufacture electronic parts under their own logo, name, or trademark. The types of product this standard applies to is limited to monolithic microcircuits, hybrid microcircuits and discrete semiconductor products. Committee(s): JC-13 Free download. Registration or login required. |
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APPLICATION THERMAL DERATING METHODOLOGIES: |
JEP149.01 | Jan 2021 |
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Free download. Registration or login required. |