Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # | Date |
|---|---|---|
200-Pin DDR2 SDRAM Unbuffered SODIMM Design Specification |
MODULE4.20.11 | Jun 2008 |
Release No. 18. Item 2168.01 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNSThis is an editorial revision, details can be found in Annex F. |
JEP162A.01 | Jan 2021 |
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Free download. Registration or login required. |
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GUIDE FOR THE PRODUCTION AND ACQUISITION OF RADIATION-HARDNESS ASSURED MULTICHIP MODULES AND HYBRID MICROCIRCUITS: |
JEP133C | Jan 2010 |
A revised and expanded publication for suppliers and users of radiation hardness assured (RHA) multichip modules (MCMs) and hybrid microcircuits, is now available. The document provides guidance as to how to achieve, maintain and ensure required levels of radiation-hardness given the fact that the constituent dice can have different levels of hardness assurance. It also describes how to deal with the various radiation hardness situations that an MCM/Hybrid developer, procuring activity or user will encounter. The guide is intended to supplement three relevant performance specifications: MIL-PRF-38534, MIL-PRF-38535 and MIL-PRF-19500. Committee(s): JC-13.5, JC-13.4 Free download. Registration or login required. |
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214-Pin DDR2 SDRAM Unbuffered MicroDIMM Design Specification |
MODULE4.20.12 | Apr 2004 |
Release No. 14 Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Part Model Guidelines for Electronic-Device Packages – XML Requirements |
JEP30F | Feb 2025 |
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure. For more information visit the main JEP30 webpage. Free download. Registration or login required. |
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PartModel Design Rule Kits Guidelines for Electronic-Device Packages – XML Requirements |
JEP30-K100 | Feb 2025 |
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the “Design Kit” subsection of the Part Model. For more information visit the main JEP30 webpage. Free download. Registration or login required. |
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FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES |
JEP122H | Sep 2016 |
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. Committee(s): JC-14.2 Available for purchase: $163.00 Add to Cart Paying JEDEC Members may login for free access. |
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Numerical Analysis Guidelines for Microelectronics Packaging Design and Reliability |
IPC/JEDEC9301-2018 | Dec 2018 |
This document is an effort to standardize and document some of the basic tenets of a typical Finite Element Analysis (FEA) model. The intent of this document is to help educate new designers (and in some cases even experienced designers) on the basic information and best practices that should be captured and provided to technical reviewers of the results of FEA data. Committee(s): JC-14.1 Free download. Registration or login required. |
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