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Title	Document #	Date
Annex W, R/C W, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.07	MODULE4.20.20.W	Aug 2009
Release No. 19 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PC-2700/PC-3200 Registered DIMM Design Specification Revision 2.2	MODULE4.20.7	May 2021
Release 31. Item 2029.04 This revision contains terminology updates only. Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex A, R/C A, in 240-Pin, 72 bit-wide, PC3(L)-6400/PC3(L)-8500/PC3(L)-10600/PC3(L)-12800/PC3(L)-14900/PC3(L)-17000 DDR3 SDRAM Load Reduced DIMM Design Specification	MODULE4.20.24.A	Apr 2014
Release No. 24. Item 2192.58B Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex V, R/C V in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification	MODULE4.20.20.V	May 2011
Release No. 21 Item 2145.27 Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex N, R/C N, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2145.22	MODULE4.20.20.N	Sep 2012
Release No. 22. Item 2145.35 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
BYTE ADDRESSABLE ENERGY BACKED INTERFACE	JESD245E	Apr 2022
This standard specifies the host and device interface for a DDR4 NVDIMM-N, which is a DIMM that achieves non-volatility by copying SDRAM contents into non-volatile memory (NVM) when host power is lost using an Energy Source managed by either the module or the host. This standard is used in conjunction with JESD248. Item 2233.54G Committee(s): JC-45.6 Free download. Registration or login required.
204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-SO-DIMM Design Specification	MODULE4.20.21 Annex C	Mar 2013
Release 23. Item 2114.28 Committee(s): JC-45, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-SODIMM Design Specification	MODULE4.20.21.A	May 2011
Release No. 21 Item 2182.01 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex M, R/C M, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2145.06A	MODULE4.20.20.M	Feb 2009
Release No. 18 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-SO-DIMM Design Specification	MODULE4.20.21.B	May 2011
Release No. 21 Item 2182.02 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex H, R/C H, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.08	MODULE4.20.20.H	Aug 2009
Release No. 19 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex Y, R/C Y, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.06	MODULE4.20.20.Y	Aug 2009
Release No. 19 Committee(s): JC-45.1, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR) 5/5X	JESD209-5C	Jul 2023
This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4). Committee(s): JC-42, JC-42.6 Available for purchase: $459.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)	JESD82-31A.01	Jan 2023
Terminology update. This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required.
WIDE I/O 2 (WideIO2)	JESD229-2	Aug 2014
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required.
DDR4 SDRAM STANDARD	JESD79-4D	Jul 2021
This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H Committee(s): JC-42.3C Available for purchase: $284.00 Add to Cart Paying JEDEC Members may login for free access.
DDR5 SDRAM Release Number: Version 1.31	JESD79-5C.01	Jul 2024
Version 1.31 This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Committee(s): JC-42, JC-42.3 Available for purchase: $423.00 Add to Cart Paying JEDEC Members may login for free access.
FBDIMM: ARCHITECTURE AND PROTOCOL	JESD206.01	Feb 2023
Terminology update. This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5). Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
Low Power Double Data Rate 4 (LPDDR4)	JESD209-4E	Jun 2024
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb. Committee(s): JC-42, JC-42.6 Available for purchase: $374.00 Add to Cart Paying JEDEC Members may login for free access.
LOW POWER DOUBLE DATA RATE 2 (LPDDR2)	JESD209-2F	Jun 2013
This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01G. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Free download. Registration or login required.
Addendum No. 1 to JESD79-4, 3D STACKED DRAM	JESD79-4-1B	Feb 2021
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G Committee(s): JC-42.3C Free download. Registration or login required.

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