Standards & Documents Search

Release No. 14

Committee(s): JC-42, JC-45

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release 22. Item 2227.03A

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release 22

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 13

Committee(s): JC-42.5

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release 22. Item 2189.17

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 21
Item 2182.02

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 21
Item 2182.01

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 31. Item 2131.03, 2078.04, 2131.06

This revision contains terminology updates only.

Committee(s): JC-45, JC-45.2, JC-45.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release 22. Item 2082.94A

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G

Committee(s): JC-42.3C

Free download. Registration or login required.

Release No. 21
Item 2082.28B, 2082.69, 2082.78, 2082.90

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

This table briefly describes the changes made to this standard, JESD21-C, Release 29, compared to its predecessor, JESD21C, Release 28.

Committee(s): JC-42.2, JC-42.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 21
 Item 2082.29B, 2082.70, 2082.80, 2082.91

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 24. Item 2192.54

Committee(s): JC-45.4

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 21
Item 2082.56B, 2082.72, 2082.81, 2082.92

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 18

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 21

Item 2082.93

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 24. Item 2192.68

Committee(s): JC-45.4

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 18

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1
Device Type Identifier: LP-DIMM Revision 1.0

This Annex describes the serial presence detect (SPD) values for all LPDDR modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in Section 2, with the exception of bytes 128~255 which are documented in separate sections, one for each family of module types. Further description of Byte 2 is found in Annex A of the SPD standard. Item 2254.01

Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 21
Item 2145.27

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 19

Committee(s): JC-45.1, JC-45

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 2099.01b

Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-42.3

Available for purchase: $247.00 Add to Cart

Paying JEDEC Members may login for free access.

Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of JESD21C. Item 2207.11

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Terminology update.

This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-40.4

Free download. Registration or login required.

Version 1.31

This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4).

Committee(s): JC-42, JC-42.3

Available for purchase: $423.00 Add to Cart

Paying JEDEC Members may login for free access.

Terminology update.
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications.

The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.3, JC-40.4

Free download. Registration or login required.

This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4).

Committee(s): JC-42, JC-42.6

Available for purchase: $459.00 Add to Cart

Paying JEDEC Members may login for free access.