Standards & Documents Search

Displaying 181 - 240 of 1471 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM APPLICATIONS	JESD82-17.01	Feb 2023
(Terminology update.) This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40, JC-40.3 Free download. Registration or login required.
FBDIMM: ARCHITECTURE AND PROTOCOL	JESD206.01	Feb 2023
Terminology update. This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5). Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES	JESD82-22.01	Feb 2023
Terminology update. This device is a one-chip spectrum analyzer that operates in the frequency range from 1 to 2 GHz.It requires no external components except some filtering of the voltage supply (one inductor, one bypass capacitor). The frequency of the VCO is adjusted by an internal DAC. No PLL loop is used to lock the VCO to a reference frequency. A counter is used to determine the VCO frequency. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DEFINITION OF THE SSTU32864 1.8 V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS:	JESD82-7A.01	Feb 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS	JESD82-29A.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.3, JC-40.4 Free download. Registration or login required.
DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-24.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar high density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410 MHz. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS:	JESD82-3B.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTVN16857 14-bit SSTL_2 registered buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM applications. Committee(s): JC-40, JC-40.3 Free download. Registration or login required.
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS:	JESD82-6A.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the 32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. Committee(s): JC-40 Free download. Registration or login required.
DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)	JESD82-31A.01	Jan 2023
Terminology update. This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required.
LRDIMM DDR3 MEMORY BUFFER (MB)	JESD82-30.01	Jan 2023
Terminology update. The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-25.01	Jan 2023
Terminology update. This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS	JESD82-26.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUB32868 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD Release Number: C.01 - Terminology update	JESD212C.01	Jan 2023
Terminology update. This document defines the Graphics Double Data Rate 5 (GDDR5) Synchronous Graphics Random Access Memory (SGRAM), including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC standard compatible 512 Mb through 8 Gb x32 GDDR5 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR5 SGRAM vendors providing JEDEC standard compatible devices. Some aspects of the GDDR5 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. Item 1733.70B Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3C Free download. Registration or login required.
DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-23.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S869 and SSTUA32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. The SSTUA32S869 and SSTUA32D869 are identical in functionality to the SSTU32S869 and SSTU32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz. Committee(s): JC-40 Free download. Registration or login required.
Joint ESDA/JEDEC - CDM Technical User Guide	JTR002-01-22	Jan 2023
This report only covers the procedures and requirements specified in ANSI/ESDA/JEDEC JS-002. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
FBDIMM: ADVANCED MEMORY BUFFER (AMB)	JESD82-20A.01	Jan 2023
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
HIGH BANDWIDTH MEMORY (HBM3) DRAM	JESD238A	Jan 2023
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42, JC-42.2 Free download. Registration or login required.
Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs	JEP183A	Jan 2023
This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. Committee(s): JC-70.1 Free download. Registration or login required.
Guidelines for Gate Charge (QG) Test Method for SiC MOSFET	JEP192	Jan 2023
This publication defines a QGS, TOT, QGD and QGS, TH which can be extracted from a measured QG waveform for SiC MOSFETs. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS	JEP163A	Jan 2023
This publication is a guideline to assist manufacturers of integrated circuits in defining conditions for burn-in and life test of their products to meet quality and reliability performance requirements of MIL-PRF-38535. Committee(s): JC-13, JC-13.2 Free download. Registration or login required.
Survey On Latch-Up Testing Practices and Recommendations for Improvements	JEP193	Jan 2023
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
THERMAL SHOCK	JESD22-A106B.02	Jan 2023
This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)	J-STD-020F	Dec 2022
The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices	J-STD-035A	Dec 2022
This method provides users with an acoustic microscopy process flow for detecting anomalies (delaminations, cracks, mold compound voids, etc.) nondestructively in encapsulated electronic devices while achieving reproducibility. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
PROCESS CHARACTERIZATION GUIDELINE	JEP132A.01	Dec 2022
This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool. Committee(s): JC-13 Free download. Registration or login required.
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS	JESD47L	Dec 2022
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. Committee(s): JC-14, JC-14.3 Available for purchase: $87.38 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Secure Serial Flash Bus Transactions Release Number: Version 1.0	JESD254	Dec 2022
This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure. Patents(): Infineon- US 10868679B1 and Micron- US 9009394B2 Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
GUIDELINES FOR COMBINING CIE 127-2007 TOTAL FLUX MEASUREMENTS WITH THERMAL MEASUREMENTS OF LEDS WITH EXPOSED COOLING SURFACE	JESD51-52A	Nov 2022
This document is intended to be used in conjunction with the JESD51-50 series of standards, especially with JESD51-51 (Implementation of the Electrical Test Method for the Measurement of Real Thermal Resistance and Impedance of Light-emitting Diodes with Exposed Cooling Surface) document. This present document focuses on the measurement of the total radiant flux of LEDs in combination with the measurement of LEDs's thermal characteristics: guidelines on the implementation of the recommendations of the CIE 127-2007 document are provided. Committee(s): JC-15 Free download. Registration or login required.
TEMPERATURE, BIAS, AND OPERATING LIFE	JESD22-A108G	Nov 2022
This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Customer Notification for Environmental Compliance Declaration Deviations	JESD262	Nov 2022
This standard is invoked when a supplier becomes aware that a product’s environmental compliance declaration they provided or made available to their customers had an error that might cause a customer to draw an incorrect conclusion about the compliance of the product to legal requirements. Committee(s): JC-14.4 Free download. Registration or login required.
OVERVIEW OF METHODOLOGIES FOR THE THERMAL MEASUREMENT OF SINGLE- AND MULTI-CHIP, SINGLE- AND MULTI-PN-JUNCTION LIGHT-EMITTING DIODES (LEDS)	JESD51-50A	Nov 2022
This document provides an overview of the methodology necessary for making meaningful thermal measurements on high-power light-emitting diodes (LEDs) built on single or multiple chips with one or more pn-junctions per chip. The actual methodology components are contained in separate detailed documents. Committee(s): JC-15 Free download. Registration or login required.
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES	JESD217A.01	Nov 2022
This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Committee(s): JC-14.1 Free download. Registration or login required.
IMPLEMENTATION OF THE ELECTRICAL TEST METHOD FOR THE MEASUREMENT OF REAL THERMAL RESISTANCE AND IMPEDANCE OF LIGHT-EMITTING DIODES WITH EXPOSED COOLING SURFACE	JESD51-51A	Nov 2022
The purpose of this document is to specify, how LEDs thermal metrics and other thermally-related data are best identified by physical measurements using well established testing procedures defined for thermal testing of packaged semiconductor devices (published and maintained by JEDEC) and defined for characterization of light sources (published and maintained by CIE – the International Commission on Illumination). Committee(s): JC-15 Free download. Registration or login required.
Serial NOR Security Hardware Abstraction Layer	JESD261	Nov 2022
This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device. Committee(s): JC-42.4 Free download. Registration or login required.
SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)	JEP164	Oct 2022
This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology. Committee(s): JC-14.3 Free download. Registration or login required.
STANDARD - DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5	PS-005B	Oct 2022
This standard defines the form, fit and function of DDR5 connectors for U/R/LR modules supporting channels with transfer rates up to 6.4 GT/S. It contains mechanical, electrical and reliability requirements for connector mated to a module with nominal thickness of 1.27 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the DDR5 connectors in client and server platforms. Item 11.14-213S Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
TERMS, DEFINITIONS AND UNITS GLOSSARY FOR LED THERMAL TESTING	JESD51-53A	Oct 2022
This document provides a unified collection of the commonly used terms and definitions in the area of LED thermal measurements. The terms and definitions provided herein extend beyond those used in the JESD51 family of documents, especially in JESD51-13, in order to include other often used terms and definitions in the area of light output measurements of LEDs. Definitions, symbols and notations regarding light output measurements used here are consistent with those defined in JESD77C.01 and with those defined by CIE (International Commission on Illumination), especially in the International Lighting Vocabulary, CIE S 017/E:2011 ILV and in the CIE 127-2007 document as well as in some other relevant standards of other standardization bodies from the solid-state lighting industry, e.g., ANSI/IESNA RP 16-05. Committee(s): JC-15 Free download. Registration or login required.
PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03	JESD301-2	Oct 2022
This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5100 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5100 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 336.01C Committee(s): JC-40.1 Free download. Registration or login required.
Registration - Plastic Bottom Grid Array Ball, 0.80 mm X 0.65 mm Pitch Rectangular Family Package	MO-311F	Oct 2022
Designator: PBGA-B#[#]_I0p65... Item: 11.11-1026, Access STP File for MO-311E Cross Reference: DR4.5 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES	JESD22-B130	Sep 2022
This test method is offered as a standardized procedure to determine the total dose limit of DRAMs by measuring its refresh time tRef degradation after the device is irradiated with an X-Ray dose. This test method is applicable to any packaged device that contains a DRAM die or any embedded DRAM structure. Some indirect test methods such as wafer level characterization of total dose induced changes in leakage of access transistors are not described in this standard but are permissible as long as a good correlation is established. Committee(s): JC-14.1 Free download. Registration or login required.
Guideline for Evaluating dv/dt Robustness of SiC Power Devices, Version 1.0	JEP190	Aug 2022
This document provides stress procedures, general failure criteria and documentation guidelines such that the dv/dt robustness can be demonstrated, evaluated and documented. This document gives examples for test setups which can be used and the corresponding test conditions. Additionally, criteria are explained under which device manufacturers can select an appropriate test setup. Committee(s): JC-70.2 Free download. Registration or login required.
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O	JESD8-20A.01	Aug 2022
Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 Committee(s): JC-16 Free download. Registration or login required.
Registration - Plastic Bottom Grid Array Ball, 0.75 MM x 0.73 MM Pitch Rectangular Family Package	MO-353A	Aug 2022
Item 11-993 Designator: PBGA-B#[#]_I0p73... Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Multi Connector 32 Pin, 1.00 MM Pitch 19.35 MM x 21.00 MM Socket	SO-031A	Aug 2022
Item 11.14-209A Designator: PMXC-G32[39]_1p0-R19p35x21p0Z3p2-N23p4T# Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Silicon Bottom Grid Array Column, 0.048 mm x 0.055 mm Pitch Square Package	MO-349A.01	Aug 2022
Item: 11.4-996E Designator: SBGA-M7775[23828]_D0p073... Item: 11.4-996 Access STP Files for MO-349A Cross Reference: DR4.26 Committee(s): JC-11.4 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Bottom Grid Array Ball, 0.65 MM Pitch Rectangular Family Package	MO-246I	Aug 2022
Designator: PBGA-B#[#]_I0p65... Item: 11.11-1024, Access STP Files for MO-246I Cross Reference: N/A Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Multi Flange Mount Rectangular Family	TO-247F	Aug 2022
Item 11.10-460 Designator: PMFM K#_I... Committee(s): JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension, Version 1.0 Status: Superseded	JESD231	Aug 2022
JESD231 was superseded by the renumbered JESD220-4 Version 1.01. Committee(s): JC-64.1
Universal Flash Storage Host Controller Interface (UFSHCI), Version 4.0 Status: Superseded December 2024 by JESD223F	JESD223E	Aug 2022
NOTE: This document has been superseded by JESD223F published in December 2024, but remains available for reference purposes. Committee(s): JC-64.1 Available for purchase: $163.00 Add to Cart Paying JEDEC Members may login for free access.
UNIVERSAL FLASH STORAGE, Version 4.0 Status: Superseded December 2024 by JESD220G	JESD220F	Aug 2022
NOTE: This document has been superseded by JESD220G published in December 2024, but remains available for reference purposes. Committee(s): JC-64.1 Available for purchase: $369.00 Add to Cart Paying JEDEC Members may login for free access.
LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES	JEP160A	Aug 2022
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
DDR5 UDIMM Raw Card Annex A Release Number: Version 1.0	JESD308-U0-RCA	Jul 2022
This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card A Annex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A Committee(s): JC-45.3 Free download. Registration or login required.
Registration - Plastic Dual Small Outline, 1.00 MM pitch5.48 MM width Rectangular Family Package	MO-351A	Jun 2022
PDSO-G10_I1p)... Item 11.11-1005 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
POD125 - 1.25 V PSEUDO OPEN DRAIN I/O	JESD8-30A.01	Jun 2022
Editorial Terminology Update. This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
POD135 - 1.35 V PSEUDO OPEN DRAIN I/O	JESD8-21C.01	Jun 2022
Editorial, Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B Committee(s): JC-16 Free download. Registration or login required.
JEDEC COMMITTEE SPECIFIC ADDITIONAL POLICIES	JM12B	Jun 2022
In some cases, JEDEC Committees have established additional policies and guidelines to facilitate the operation of a particular committee. Additional policies and guidelines are set forth here as an addendum to JM21 to facilitate the operation of particular committees. These policies are in addition to the requirements set forth in JM21 and in no case shall these additions contradict or supersede the requirements in JM21. Committee(s): JC-JEDC Free download. Registration or login required.
SOLID-STATE DRIVE (SSD) ENDURANCE WORKLOADS	JESD219A.01	Jun 2022
Terminology update, see Annex. This standard defines workloads for the endurance rating and endurance verification of SSD application classes. These workloads shall be used in conjunction with the Solid State Drive (SSD) Requirements and Endurance Test Method standard, JESD218. Also see JESD219A_MT and JESD219A_TT for the supporting trace files. Committee(s): JC-64, JC-64.8 Free download. Registration or login required.
EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES	JESD251C	May 2022
This standard specifies the eXpanded Serial Peripheral Interface (xSPI) for Non Volatile Memory Devices, which provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is primarily for use in computing, automotive, Internet Of Things (IOT), embedded systems and mobile systems, between host processing and peripheral devices. The xSPI electrical interface can deliver up to 400 MBytes per second raw data throughput. Item 1775.74. Committee(s): JC-42.4 Free download. Registration or login required.
Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs	SPD4.1.3-01	May 2022
Release No. 19.01. Item 1739.02E, Terminology update. This standard defines the specifications of interface parameters, signaling protocols, and features for Serial Presence Detect (SPD) EEPROMs as used for memory module applications. Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Mobile Platform Memory Module Thermal Sensor Component Specification	MODULE4.7	May 2022
Release No. 16. This replaces Release 15 and includes the following editorial changes: 1) Replaced master/slave with controller/target 2) Checked for presence of other sensitive words 3) Added Tables and Figures in Table of Contents (Release 15, Item 1640.07) Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Pages

JEDEC Education Series: Memory, Mobile & Modules

Standards & Documents Search

DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM APPLICATIONS

FBDIMM: ARCHITECTURE AND PROTOCOL

INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES

DEFINITION OF THE SSTU32864 1.8 V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS:

DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS

DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

DEFINITION OF THE SSTV16857 2.5 V, 14-BIT SSTL_2 REGISTERED BUFFER FOR DDR DIMM APPLICATIONS:

DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS:

DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02)

LRDIMM DDR3 MEMORY BUFFER (MB)

DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD

DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

Joint ESDA/JEDEC - CDM Technical User Guide

FBDIMM: ADVANCED MEMORY BUFFER (AMB)

HIGH BANDWIDTH MEMORY (HBM3) DRAM

Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs

Guidelines for Gate Charge (QG) Test Method for SiC MOSFET

SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS

Survey On Latch-Up Testing Practices and Recommendations for Improvements

THERMAL SHOCK

JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)

JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices

PROCESS CHARACTERIZATION GUIDELINE

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

Secure Serial Flash Bus Transactions

GUIDELINES FOR COMBINING CIE 127-2007 TOTAL FLUX MEASUREMENTS WITH THERMAL MEASUREMENTS OF LEDS WITH EXPOSED COOLING SURFACE

TEMPERATURE, BIAS, AND OPERATING LIFE

Customer Notification for Environmental Compliance Declaration Deviations

OVERVIEW OF METHODOLOGIES FOR THE THERMAL MEASUREMENT OF SINGLE- AND MULTI-CHIP, SINGLE- AND MULTI-PN-JUNCTION LIGHT-EMITTING DIODES (LEDS)

TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

IMPLEMENTATION OF THE ELECTRICAL TEST METHOD FOR THE MEASUREMENT OF REAL THERMAL RESISTANCE AND IMPEDANCE OF LIGHT-EMITTING DIODES WITH EXPOSED COOLING SURFACE

Serial NOR Security Hardware Abstraction Layer

SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)

STANDARD - DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5

TERMS, DEFINITIONS AND UNITS GLOSSARY FOR LED THERMAL TESTING

PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03

Registration - Plastic Bottom Grid Array Ball, 0.80 mm X 0.65 mm Pitch Rectangular Family Package

TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES

Guideline for Evaluating dv/dt Robustness of SiC Power Devices, Version 1.0

POD15 - 1.5 V PSEUDO OPEN DRAIN I/O

Registration - Plastic Bottom Grid Array Ball, 0.75 MM x 0.73 MM Pitch Rectangular Family Package

Registration - Plastic Multi Connector 32 Pin, 1.00 MM Pitch 19.35 MM x 21.00 MM Socket

Registration - Silicon Bottom Grid Array Column, 0.048 mm x 0.055 mm Pitch Square Package

Registration - Plastic Bottom Grid Array Ball, 0.65 MM Pitch Rectangular Family Package

Registration - Plastic Multi Flange Mount Rectangular Family

Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension, Version 1.0

Universal Flash Storage Host Controller Interface (UFSHCI), Version 4.0

UNIVERSAL FLASH STORAGE, Version 4.0

LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES

DDR5 UDIMM Raw Card Annex A

Registration - Plastic Dual Small Outline, 1.00 MM pitch5.48 MM width Rectangular Family Package

POD125 - 1.25 V PSEUDO OPEN DRAIN I/O

POD135 - 1.35 V PSEUDO OPEN DRAIN I/O

JEDEC COMMITTEE SPECIFIC ADDITIONAL POLICIES

SOLID-STATE DRIVE (SSD) ENDURANCE WORKLOADS

EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NONVOLATILE MEMORY DEVICES

Definition of the EE1002 and EE1002A Serial Presence Detect (SPD) EEPROMs

Mobile Platform Memory Module Thermal Sensor Component Specification

Pages

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: