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This document contains standard lists of values which are recommended for use in semiconductor device specification and JEDEC Registration Formats. Good reasons should exist in those cases where values are used that are not included in these lists. Formerly known as EIA-419-A, that superseded JEP74 (February 1996).

Committee(s): JC-25

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The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

Committee(s): JC-42, JC-42.3

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This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process.

Committee(s): JC-14.2

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Item 11.2-710S

Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11, JC-11.2

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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This document states the procedures for using component land side flatness during simulated reflow as an alternative to coplanarity in certain limited cases for BGA components.

Committee(s): JC-11, JC-11.11

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11, JC-11.2

JEP95 Registrations Main Page

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This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS devices.

Committee(s): JC-40.2

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STAPL is a vendor- and platform-independent language for programming and testing devices via the IEEE standard 1149.1 interface, commonly known as JTAG. STAPL enables programming of designs into programmable logic devices (PLDs) offered by a variety of PLD vendors. STAPL is also suitable for testing 1149.1-compliant devices.

Committee(s): JC-42.1

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This document is intended to be used by Original Component Manufacturers who deliver electronic components and Original Equipment Manufacturers who are the platform system integrators. It is intended to be applied prior to delivery by the OCMs and may be used by OEM system engineers and procuring activities as well as U.S Government Department of Defense system engineers, procuring activities and repair centers. This Standard establishes the instrumentation, techniques, criteria, and methods to be utilized to quantify the amount of Lead (Pb) in Tin-Lead (Sn/Pb) alloys and electroplated finishes containing at least 3 weight percent (wt%) Lead (Pb) using X-Ray Fluorescence (XRF) equipment.  Reaffirmed June 2023

Committee(s): JC-13

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This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems.

Committee(s): JC-14.2, JC-14.21

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This standard establishes a defined method and conditions for performing a temperature-humidity life test with bias applied. The test is used to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs high temperature and humidity conditions to accelerate the penetration of moisture through external protective material or along interfaces between the external protective coating and conductors or other features that pass through it. This revision enhances the ability to perform this test on a device which cannot be biased to achieve very low power dissipation.

Committee(s): JC-14, JC-14.1

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This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed.

Committee(s): JC-14, JC-14.3

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This manual establishes requirements for the preparation of standards and certain other publications of the JEDEC Solid State Technology Association.

Committee(s): JC-10

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A complete set of test methods can be obtained from Global Engineering Documents

Committee(s): JC-14.1

This standard will be useful to anyone engaged in handling semiconductor devices and integrated circuits that are subject to permanent damage due to electrostatic potentials. The standard establishes a symbol and label that will gain the attention of those persons who might inflict electrostatic damage to the device. The label which is placed on the lowest practical level of packaging contains the words 'ATTENTION - OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES'. The symbol contained in this label, which may be used on the device itself, shows a hand in a triangle with a bar through it. Formerly known as EIA-471.

Committee(s): JC-14, JC-14.3

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Release No. 9

Committee(s): JC-42.3

JESD21-C Solid State Memory Documents Main Page

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This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology.

Committee(s): JC-14.3

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A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02.

Committee(s): JC-42

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This test is used to determine the effects of bias conditions and temperature on solid state devices over time. It simulates the devices’ operating condition in an accelerated way, and is primarily for device qualification and reliability monitoring. A form of high temperature bias life using a short duration, popularly known as burn-in, may be used to screen for infant mortality related failures. The detailed use and application of burn-in is outside the scope of this document.

Committee(s): JC-14, JC-14.1

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This document provides a unified collection of the commonly used terms and definitions in the area of LED thermal measurements. The terms and definitions provided herein extend beyond those used in the JESD51 family of documents, especially in JESD51-13, in order to include other often used terms and definitions in the area of light output measurements of LEDs. Definitions, symbols and notations regarding light output measurements used here are consistent with those defined in JESD77C.01 and with those defined by CIE (International Commission on Illumination), especially in the International Lighting Vocabulary, CIE S 017/E:2011 ILV and in the CIE 127-2007 document as well as in some other relevant standards of other standardization bodies from the solid-state lighting industry, e.g., ANSI/IESNA RP 16-05.

Committee(s): JC-15

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