Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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Standard - Plastic Dual Small Outline, 1.27 mm pitch, 7.50 mm Body Width Rectangular Package Family |
MS-013G | Oct 2020 |
Designator: PDSO-G#-I1p27... Item 11.11-967(S). Committee(s): JC-11.11 Free download. Registration or login required. |
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Standard - Plastic Single-in-Line Flange-Mounted, 5 Leads. PSFM. Item 11.10-220. |
TS-001-A | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Plastic SOJ, .300 inch Body, .050 inch Lead Spacing. Item 11.11-330S. |
MS-023-A | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Side Brazed Ceramic DIPs in .300 inch, .400 inch and .900 inch Center Line Row-to-Row Spacing. Item 11.10-272. |
MS-015-A | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Single Layer Chip Carrier Family, .040 inch Terminal Spacing, Ceramic. Variations AA-AJ. Item 11.3-112. |
MS-014-A | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Small Outline J-Lead (SOJ) Family, .400 inch Wide Body. PDSO-J. Item 11.11-404S |
MS-027-A | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - SMT DDR2 DIMM Socket, Coplanarity Measurement Gauge. Item 11.14-102. |
GS-006-A | Jun 2007 |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - SMT DDR3 DIMM Socket Coplanarity Measurement Gauge. Item 11.14-124. |
GS-009A | Jan 2009 |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Square Plastic Chip Carrier Family, 1.27 mm/.050 inch Pitch. Item 11.11-252S. |
MS-018-A | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Surface Mounted Header Family, 2 Leads, Peripheral Terminals. R-PSFM-G. Item 11.10-327S. |
TS-005-A | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Tape Automated Bonding (TAB) Package Family. S-PQUC-X/TAB. |
US-001-B | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Thin Matrix Tray for Handling and Shipping of Plastic Qual Flatpack Packages (PQFP). Variations AA-AG. Item 11.5-311. |
CS-002-A | Mar 1993 |
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Free download. Registration or login required. |
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Standard - Thin Matrix Tray for Handling and Shipping PLCC Packages. Variations AA-AL. Item 11.5-312. |
CS-003-B | Apr 1993 |
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Free download. Registration or login required. |
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Standard - Thin Matrix Tray for MQFP Shipping. Item 11.5-436S |
CS-004-B | Apr 1996 |
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Free download. Registration or login required. |
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Standard - Thin Matrix Tray for TQFP. |
CS-007-A | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - Thin Small Outline Package. TSOPII Package. This revision modifies leadframe thickness for 10.16 mm body SOIC family. Item 11.11-753(S) |
MS-024H | Jun 2006 |
Committee(s): JC-11.11 Free download. Registration or login required. |
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Standard - TSOP II, 7.62 mm Body. Change to the Max. Bend Radius and Foot Angle. Item 11.11-518S |
MS-025-B | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard - TSOP II, Thin Matrix Tray for Shipping and Handling of FBGA's. Item 11.5-519. |
CS-005-B | Nov 1998 |
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Free download. Registration or login required. |
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Standard - TSOP-I, Thin Matrix Tray for Shipping and Handling. Item 11.4-437S. |
CS-008-A | Mar 1996 |
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Free download. Registration or login required. |
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STANDARD DATA TRANSFER FORMAT BETWEEN DATA PREPARATION SYSTEM AND PROGRAMMABLE LOGIC DEVICE PROGRAMMER: |
JESD3-C | Jun 1994 |
This standard was developed to prevent the proliferation of data transfer formats that occurred with microprocessor development systems. The focus of the standard is on field programmable devices and their support tools. It is not intended for other types of semicustom logic devices or other types of fabrication or testing equipment. Committee(s): JC-42.1 Free download. Registration or login required. |
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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION): |
JESD76-2 | Jun 2001 |
This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (normal range) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION): |
JESD76-1 | Jun 2001 |
This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (nominal) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES: |
JESD76-3 | Aug 2001 |
This standard continues the voltage specification migration to the next level beyond the 1.8 V specification already established. The purpose is to provide a standard for 1.5 V nominal supply voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Free download. Registration or login required. |
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STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES: |
JESD36 | Jun 1996 |
This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C.Status: RescindedApr-85 |
JEP102 | Jan 1978 |
Committee(s): JC-42 |
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STANDARD FOR CHAIN DESCRIPTION FILE: |
JESD32 | Jun 1996 |
This document provides a standard for describing an ISP device chain, opening up the possibility for third-party companies to provide value-added ISP software. The purpose of the Chain Description File is to describe the configuration of a programming chain made up of devices that can be connected in some serial fashion. No assumptions are made about how data is used by the device, nor about the nature or configuration of the control signals that affect programming. It will support devices configured using electrically-erasable(EE), Flash, SRAM, or any other reconfigurable cell. For devices programmed via an IEEE programmable devices in the same chain. Committee(s): JC-42.1 Free download. Registration or login required. |
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STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVE FOR REGISTERED DDR2 DIMM APPLICATION |
JESD82-8.01 | Feb 2004 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a íCU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a íCU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS |
JESD82-21 | Jan 2007 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS |
JESD82-15 | Nov 2005 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CUA878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS |
JESD82-18A | Jan 2007 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS: |
JESD82-4B.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS: |
JESD64-A | Oct 2000 |
The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES: |
JESD80 | Nov 1999 |
The purpose of this standard is to provide a standard for 2.5 V nominal supply-voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This standard defines dc interface parameters and test loading for CMOS digital logic family based on 2.5 V (nominal) power supply levels at 2.5 V input tolerance. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS: |
JESD73-2 | Aug 2001 |
This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices with integrated charge pumps. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this standard is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES: |
JESD73-1 | Aug 2001 |
This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this document is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH: |
JESD73-3 | Nov 2001 |
This standard provides a set of uniform data sheet parameters for the description of a single 10-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay. Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH: |
JESD73-4 | Nov 2001 |
This standard provides a set of uniform data sheet parameters for the description of a dual 5-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay. Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES: |
JESD54 | Feb 1996 |
The purpose is to provide a standard of BiCMOS Logic series specifications to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:Release Number: Pt 1 |
JESD20 | Jan 1990 |
This standard describes electrical parameters for this class of CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:Release Number: Pt 2 |
JESD20 | Jan 1990 |
This standard describes electrical parameters for this class of CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES: |
JESD7-A | Aug 1986 |
This standard provides uniformity, multiplicity of sources, eliminate confusion, and ease of device specification and design by users for HC, and HCT CMOS devices. This standard specifies electrical parameters. It also includes appendices listing part numbers. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS: |
JESD82-2 | Jul 2001 |
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION |
JESD82-5 | Jul 2002 |
This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC: |
JESD18-A | Jan 1993 |
The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of '54/74FCTXXXX' series fast CMOS TTL compatible devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES: |
JESD52 | Nov 1995 |
This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES: |
JESD55 | May 1996 |
The purpose is to provide a standard of BiCMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR FAILURE ANALYSIS REPORT FORMAT: |
JESD38 | Dec 1995 |
This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets. Committee(s): JC-14.6 Free download. Registration or login required. |
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STANDARD FOR MEASURING FORWARD SWITCHING CHARACTERISTICS OF SEMICONDUCTOR DIODES:Status: ReaffirmedApril 2005 |
JESD286-B | Feb 2000 |
This method updates the standard procedure for characterizing the switching of signal or switching diodes when a step function of forward current is applied. The objective is to provide a standard so that accurate comparisons can be made. Formerly known as EIA-286-A (February 1991), ANSI/EIA-286-A-1991. Became JESD286-B after revision, February 2000. Committee(s): JC-22.4 Free download. Registration or login required. |
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STANDARD FOR SELENIUM SURGE SUPPRESSORS: |
TENTSTD12 | Nov 1973 |
The suppresser furnished under this standard shall be a product that has been tested and meets the definitions and minimum requirements specified herein. Committee(s): JC-22.5 |
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STANDARD FOR THE MEASUREMENT OF CREStatus: Reaffirmed April 1981, April 1999, March 2009 |
JESD340 | Nov 1967 |
This standard offers an easily measured parameter which is one of the significant characteristics in determining the stability of a transistor intended for small-signal operation. The measurement technique allows rapid testing. Its correlation to AC stability will help to establish the interchangeability of a device. Formerly known as RS-340 and/or EIA-340. Committee(s): JC-25 Free download. Registration or login required. |
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STANDARD FOR THE MEASUREMENT OF SMALL-SIGNAL TRANSISTOR SCATTERING PARAMETERS:Status: ReaffirmedApril 1999, March 2009 |
JESD435 | Apr 1976 |
This standard specifies the standard for the measurement of small-signal transistor scattering parameters. Formerly known as RS-435 and/or EIA-435 Committee(s): JC-25 Free download. Registration or login required. |
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STANDARD LIST OF VALUES TO BE USED IN POWER TRANSISTOR DEVICE REGISTRATION AND MINIMUM DIFFERENCES FOR DISCRETENESS OF REGISTRATIONS - SUPERSEDED BY EIA-419-A, February 1996.Status: Rescinded |
JEP74 | Jan 1969 |
Committee(s): JC-25 |
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STANDARD LIST OF VALUES TO BE USED IN SEMICONDUCTOR DEVICE SPECIFICATIONS AND REGISTRATION FORMAT:Status: ReaffirmedMarch 2001 |
JESD419-A | Oct 1980 |
This document contains standard lists of values which are recommended for use in semiconductor device specification and JEDEC Registration Formats. Good reasons should exist in those cases where values are used that are not included in these lists. Formerly known as EIA-419-A, that superseded JEP74 (February 1996). Committee(s): JC-25 Free download. Registration or login required. |
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STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD: |
JESD37A | Aug 2017 |
This standard details techniques for estimating the values of a two parameter lognormal distribution from complete lifetime data (all samples in an experiment have failed) or singly right-censored lifetime data (the experiment have failed) or singly right-censored lifetime data gathered from rapid stress test; however, not all types of failure data can be analyzed with these techniques. Committee(s): JC-14.2 Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODE |
JEP106BK | Sep 2024 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Free download. Registration or login required. |
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STANDARD MEASURMENTS OF THE ELECTRICAL CHARACTERISTICS OF SEMICONDUCTOR INTEGRATED CIRCUITSStatus: RescindedOct-84 |
JEB6 | Jan 1966 |
Committee(s): JCJEDC |
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STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:Status: Reaffirmed 4/17/23 |
JESD63 | Apr 2023 |
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process. Committee(s): JC-14.2 Free download. Registration or login required. |
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STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE:Status: Reaffirmed October 2012, September 2018 |
JESD33B | Feb 2004 |
This newly revised test method provides a procedure for measuring the temperature coefficient of resistance, TCR(T), of thin-film metallizations used in microelectronic circuits and devices. Procedures are also provided to use the TCR(T) to determine the temperature of a metallization line under Joule-heating conditions and to determine the ambient temperature where the metallization line is used as a temperature sensor. Originally, the method was intended only for aluminum-based metallizations and for other metallizations that satisfy the linear dependence and stability stipulations of the method. The method has been revised to make it explicitly applicable to copper-based metallizations, as well, and at temperatures beyond where the resistivity of copper is no longer linearly dependent on temperature (beyond approximately 200 °C). Using the TCR(T) measured for copper in the linear-dependent region, a factor is used to correct the calculated temperature at these higher temperatures. Committee(s): JC-14.2 Free download. Registration or login required. |
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Standard Practices and Procedures - Change Record Methodology |
SPP-021A | Jan 2006 |
Item 11.2-710S Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Definition of DAMBAR Protrusion and Intrusion. |
SPP-006 | |
Committee(s): JC-11 Free download. Registration or login required. |
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