Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
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PLASTIC DUAL SMALL OUTLINE, GULL WING, 2.00 MM PITCH, RECTANGULAR PACKAGE |
MO-359B | Jul 2024 |
Designator: H-PDSO-G12_12p0-12p0x9p4Z2p8 Item No: 11-1049
Free download. Registration or login required. |
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Style Manual for Standards and Other Publications of JEDEC |
JM7A | Jul 2024 |
This manual establishes requirements for the preparation of standards and certain other publications of the JEDEC Solid State Technology Association. Committee(s): JC-10 Free download. Registration or login required. |
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DDR5 SDRAMRelease Number: Version 1.31 |
JESD79-5C.01 | Jul 2024 |
Version 1.31 This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Available for purchase: $423.00 Add to Cart Paying JEDEC Members may login for free access. |
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PLASTIC FLANGE MOUNT, THROUGH-HOLE, 2.54 MM PITCH RECT PACKAGE (TRANSISTOR) |
TO-282A | Jun 2024 |
Package Designator: PMDF-T5_I2p54... Item # 11-1058 Patents(): Owners: - Otremba, Ralf - Kasztelan, Christian - Fuergut, Edward - Lee, Teck Sim - Wang, Lee Shuang - Kuek, Hsieh Ting - Murugan, Sanjay Kumar Company: - Infineon Technologies AG, 85579 Neubiberg, DE Patent Number (Germany): - DE 102015109073 B4 Title: - Free download. Registration or login required. |
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MCP and Discrete e•MMC, e•2MMC, and UFSRelease Number: 33 |
MCP3.12.1-1 | Jun 2024 |
Item 142.12 This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.
Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1 |
JEP200 | Jun 2024 |
This document provides guidelines for test methods and circuits to be used for measuring switching energy loss due to output capacitance hysteresis in semiconductor power devices. Committee(s): JC-70, JC-70.1, JC-70.2 Free download. Registration or login required. |
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DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH, MICROELECTRONIC ASSEMBLY |
MO-358B | Jun 2024 |
Designator: XBNA-N#_I1p0_... Item No: 14-229 Free download. Registration or login required. |
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JEDEC® Memory Module Label – for Compute Express Link® (CXL®)Release Number: 1.1 |
JESD405-1B | Jun 2024 |
This standard defines the labels that shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. Committee(s): JC-45 Free download. Registration or login required. |
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Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA) |
JEP170A | Jun 2024 |
This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices. Free download. Registration or login required. |
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Information Requirements for the Qualification of Solid State Devices |
JESD69D | Jun 2024 |
This standard defines the requirements for the device qualification package, which the supplier provides to the customer. Free download. Registration or login required. |
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Board Level Drop Test Method of Components for Handheld Electronic Products |
JESD22-B111A.01 | Jun 2024 |
This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components. Free download. Registration or login required. |
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DDR5 Registering Clock Driver Definition (DDR5RCD04) |
JESD82-514.01 | Jun 2024 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054. Free download. Registration or login required. |
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Low Power Double Data Rate 4 (LPDDR4) |
JESD209-4E | Jun 2024 |
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb. Available for purchase: $374.00 Add to Cart Paying JEDEC Members may login for free access. |
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PLASTIC BOTTOM GRID, ARRAY BALL, 0.50 MM X 0.70 MM PITCH RECTANGULAR FAMILY PACKAGE |
MO-360A | May 2024 |
Item #11-1048A Package Designator: PBGA-B#[#] I0p5... Free download. Registration or login required. |
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PLASTIC QUAD FLATPACK, 28 TERMINAL PACKAGE |
MO-339B | May 2024 |
Item 11-1054 Package Designator: PQFP-N28_I4p0... Free download. Registration or login required. |
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PLASTIC DUAL SMALL OUTLINE, GULL WING, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE) |
DO-215E | May 2024 |
Package Designator: P-PDSO-G2... Committee(s): JC-11, JC-11.1, JC-11.10 Free download. Registration or login required. |
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SHIPPING AND HANDLING TRAY FOR LPDDR5 CAMM2 MODULE |
CO-041A | Apr 2024 |
Item #11.5-1057 Free download. Registration or login required. |
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Marking, Symbols, and Labels of Leaded and Lead-Free Terminal Finished Materials Used in Electronic Assembly |
J-STD-609C.01 | Apr 2024 |
This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd level terminal finish or material. Free download. Registration or login required. |
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SHIPPING AND HANDLING TRAY FOR CAMM2 CONNECTOR |
CO-040B | Apr 2024 |
Designator: N/A Item #: 11.5-1041 Free download. Registration or login required. |
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PLASTIC DUAL SMALL OUTLINE, FLAT LEAD, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE) |
DO-219D | Apr 2024 |
Free download. Registration or login required. |
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PMIC5020 Power Management IC StandardRelease Number: Version 1.0.1 |
JESD301-4 | Apr 2024 |
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Free download. Registration or login required. |
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Procedure for Reliability Characterization of Metal-Insulator-Metal Capacitors |
JEP199 | Apr 2024 |
This document defines the standards for achieving Reliability certification and qualification of on-chip MIM Capacitors and MIS Trench Capacitors. Free download. Registration or login required. |
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PLASTIC BOTTOM GRID, ARRAY BALL, 0.60 MM X 0.0675 MM PITCH RECTANGULAR FAMILY PACKAGE |
MO-361A | Apr 2024 |
Designator: PBGA--B264[294]_I0p60-R8p7X14p4Z1p0-C0p3Z# Item: 11-1050 Free download. Registration or login required. |
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Gate Dielectric Breakdown |
JESD263 | Mar 2024 |
This document describes procedures developed for estimating the overall integrity of gate dielectrics. JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92. Free download. Registration or login required. |
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JEDEC® Memory Module Reference Base Standard – for Compute Express Link® (CXL®) |
JESD317A | Mar 2024 |
This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL-attached memory modules. Committee(s): JC-45 Free download. Registration or login required. |
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SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI) |
JESD255 | Mar 2024 |
The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus. Free download. Registration or login required. |
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Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress |
JEP154A | Mar 2024 |
This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. Free download. Registration or login required. |
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Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices |
JESD625C.01 | Mar 2024 |
This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). Free download. Registration or login required. |
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DDR5 Clock Driver Definition (DDR5CKD01)Release Number: Version 1.1 |
JESD82-531A.01 | Feb 2024 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5, Free download. Registration or login required. |
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SHIPPING AND HANDLING TRAY FOR DDR5 SODIMM MICROELECTRONIC ASSEMBLY |
CO-037A | Jan 2024 |
Designator: N/A Item #: 11.5-995
Free download. Registration or login required. |
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Registration - Plastic Multi Small Outline, 17 Terminal, 1.20 mm Pitch Package. PMSO-E17. |
MO-332B | Jan 2024 |
Package Designator: PMSO-E17_I1p2... Item 11.11-1046, Free download. Registration or login required. |
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Definition of “Low-Halogen” For Electronic Products |
JS709D | Jan 2024 |
This standard provides terms and definitions for “low-halogen” electronic products. Free download. Registration or login required. |
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DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common SpecificationRelease Number: Version 1.0 |
JESD323 | Jan 2024 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Clocked, Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CUDIMMs). These DDR5 Clocked Unbuffered DIMMs (CUDIMMs) are intended for use as main memory when installed in Computers. Free download. Registration or login required. |
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DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common StandardRelease Number: Version 1.1 |
JESD308A | Jan 2024 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers. Free download. Registration or login required. |
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DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common SpecificationRelease Number: Version 1.0 |
JESD324 | Jan 2024 |
This standard defines the electrical and mechanical requirements for 262-pin, 1.1 V (VDD), Clocked Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM CSODIMMs). These DDR5 CSODIMMs are intended for use as main memory when installed in Computers, laptops and other systems. Free download. Registration or login required. |
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PLASTIC DUAL SMALL OUTLINE, SURFACE TERMINAL, WETTABLE FLANK PACKAGE |
MO-340D | Dec 2023 |
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04
Item: 11-1044 Cross Reference: DR4.8, DR4.16, DR4.20 Patents(): Nexperia BV: 8809121B2 Committee(s): JC-11.11 Free download. Registration or login required. |
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Serial Interface for Data Converters |
JESD204D | Dec 2023 |
This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document. Committee(s): JC-16 Free download. Registration or login required. |
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XFM Device, Version 2.0 |
JESD233A | Dec 2023 |
This standard specifies the mechanical and electrical characteristics of the XFM removable memory Device. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Free download. Registration or login required. |
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Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices |
JEP150A | Dec 2023 |
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices. Free download. Registration or login required. |
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Power Cycling |
JESD22-A122B | Nov 2023 |
This Test Method establishes a uniform method for performing solid state device package power cycling stress test. Free download. Registration or login required. |
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Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature |
JESD22-B112C | Nov 2023 |
This test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of thermal conditions experienced during the surface-mount soldering operation. Free download. Registration or login required. |
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IC LATCH-UP TEST |
JESD78F.02 | Nov 2023 |
This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Free download. Registration or login required. |
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Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications |
JESD22-B121 | Nov 2023 |
This test method covers X-ray imaging for terrestrial applications on packaged devices. Free download. Registration or login required. |
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Zoned Storage for UFS |
JESD220-5 | Nov 2023 |
The purpose of this standard is to describe Zoned Storage for UFS, which enables higher bandwidth, lower latency and to reduce write amplification. Patents(): Huawei 201911209032.1; 116166570,A Memory Technologies LLC 101952808 104657284 2248023 3493067 602009056490.0 602009064847.0 HK1210296 5663720 6602823 10-1281326 10-1468824 2248023 3493067 2248023 3493067 8307180 8601228 9063850 9367486 10540094 11550476 Free download. Registration or login required. |
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Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension |
JESD220-4 Version 1.01 | Nov 2023 |
This standard specifies the extension specification of the UFS electrical interface and the memory device. PLEASE NOTE: Revision and renumbering of JESD231 Version 1.0, August 2022 Free download. Registration or login required. |
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Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices |
JEP198 | Nov 2023 |
This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches. Free download. Registration or login required. |
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Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices |
JEP197 | Nov 2023 |
This publication provides guidance to SiC product suppliers and related power electronic industries in their evaluation of bipolar degradation mechanism in SiC power devices. Free download. Registration or login required. |
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A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces |
JEP196 | Nov 2023 |
This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. Free download. Registration or login required. |
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ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema |
JEP181_Schema_R2p0 | Nov 2023 |
In conjunction with JEP181A, for user support this file is the entire “XML Requirements Schema”. Committee(s): JC-15 Free download. Registration or login required. |
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ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements |
JEP181A | Nov 2023 |
This publication establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. Committee(s): JC-15 Free download. Registration or login required. |
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JEDEC Manual of Organization and Procedure |
JM21V | Nov 2023 |
This Manual sets forth the mission and requirements of JEDEC as an independent incorporated Association governed by a Board of Directors.
Committee(s): JC-BOD Free download. Registration or login required. |
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Design Requirements - BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM |
DR-4.50 | Nov 2023 |
BALL GRID ARRAY PACKAGE Item 2-1038 Committee(s): JC-11.2 Free download. Registration or login required. |
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PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD) |
JESD49B.01 | Oct 2023 |
This standard facilitates the procurement and use of semiconductor die products provided in bare or bumped die form, and provides requirements and guidance to die suppliers as to the levels of as-delivered performance, quality and reliability expected. It also reflects the special needs of die product customers in terms of design and application data. Committee(s): JC-13 Free download. Registration or login required. |
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JEDEC COMMITTEE SCOPE MANUAL |
JM18U | Oct 2023 |
The JEDEC Board of Directors is responsible for establishing appropriate committees to conduct its standardization activities. This publication identifies the service and product committees established by the Board of Directors and defines their scopes. Committee(s): JC-COUN Free download. Registration or login required. |
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Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 33 |
MODULE4.20.25.K.01 | Aug 2023 |
This revision is to add R/C K1 for up to Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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PLASTIC QUAD FLATPACK 1.27 MM PITCH, 5.00 MM X 6.00 MM RECTANGULAR FAMILY PACKAGE |
MO-356A | Aug 2023 |
Designator: PQFP-B#[#]_Ip27... Item #: 11-1037 Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch Rectangular Family |
MO-276U | Aug 2023 |
Designator: PBGA-B#[#]I0p5...
Item JC11.11-1036 Cross Reference: DR4.5 Committee(s): JC-11.11 Free download. Registration or login required. |
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TS511X, TS521X Serial Bus Thermal Sensor Device Standard |
JESD302-1A | Aug 2023 |
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document. Committee(s): JC-40.1 Free download. Registration or login required. |
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REGISTRATION - Upper PoP, Plastic Bottom Grid Array Ball, 0.40 mm Pitch Rectangular Family Package |
MO-344B | Aug 2023 |
Designator: PBGA-B#[#]_I0p40... Cross Reference: DR4.18 Committee(s): JC-11 Free download. Registration or login required. |
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Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package |
MO-341B | Aug 2023 |
Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1
Item: 11-1030 Committee(s): JC-11.11 Free download. Registration or login required. |