Standards & Documents Search

Item #11-1048A

Package Designator: PBGA-B#[#] I0p5...

Committee(s): JC-11, JC-11.11

JEP95 Registrations Main Page

Free download. Registration or login required.

Package Designator: P-PDSO-G2...

Committee(s): JC-11, JC-11.1, JC-11.10

JEP95 Registrations Main Page

Free download. Registration or login required.

This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd  level terminal finish or material.

Committee(s): JC-14, JC-14.4

Free download. Registration or login required.

Committee(s): JC-11, JC-11.11

JEP95 Registrations Main Page

Free download. Registration or login required.

This document defines the standards for achieving Reliability certification and qualification of on-chip MIM Capacitors and MIS Trench Capacitors.

Committee(s): JC-14, JC-14.2

Free download. Registration or login required.

This document describes procedures developed for estimating the overall integrity of gate dielectrics.

JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92.

Committee(s): JC-14, JC-14.2

Free download. Registration or login required.

The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus.

Committee(s): JC-42, JC-42.4

Free download. Registration or login required.

This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM).

Committee(s): JC-13, JC-14.1

Free download. Registration or login required.

Designator: N/A

Item #: 11.5-995

Committee(s): JC-11, JC-11.5

JEP95 Registrations Main Page

Free download. Registration or login required.

This standard provides terms and definitions for “low-halogen” electronic products.

Committee(s): JC-14, JC-14.4

Free download. Registration or login required.

This standard defines the electrical and mechanical requirements for 288-pin, 1.1 V (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR5 SDRAM UDIMMs). These DDR5 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in Computers.

Committee(s): JC-45, JC-45.3

Free download. Registration or login required.

Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04

Item: 11-1044

Cross Reference: DR4.8, DR4.16, DR4.20

Patents(): Nexperia BV: 8809121B2

Committee(s): JC-11.11

JEP95 Registrations Main Page

Free download. Registration or login required.

This standard specifies the mechanical and electrical characteristics of the XFM removable memory Device.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-64, JC-64.1

Free download. Registration or login required.

This Test Method establishes a uniform method for performing solid state device package power cycling stress test.

Committee(s): JC-14, JC-14.1

Free download. Registration or login required.

This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress.

This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880.

Committee(s): JC-14, JC-14.1

Free download. Registration or login required.

The purpose of this standard is to describe Zoned Storage for UFS, which enables higher bandwidth, lower latency and to reduce write amplification.

Patents(): Huawei 201911209032.1; 116166570,A Memory Technologies LLC 101952808 104657284 2248023 3493067 602009056490.0 602009064847.0 HK1210296 5663720 6602823 10-1281326 10-1468824 2248023 3493067 2248023 3493067 8307180 8601228 9063850 9367486 10540094 11550476

Committee(s): JC-64, JC-64.1

Free download. Registration or login required.

This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches.

Committee(s): JC-70, JC-70.1

Free download. Registration or login required.

This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces.

Committee(s): JC-14, JC-14.3

Free download. Registration or login required.

This publication establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format.

Committee(s): JC-15

Free download. Registration or login required.

BALL GRID ARRAY PACKAGE
BALL PITCH ≤ 0.80 MM
BODY SIZES ≤ 21 MM

Item 2-1038

Committee(s): JC-11.2

JEP95 Registrations Main Page

Free download. Registration or login required.

The JEDEC Board of Directors is responsible for establishing appropriate committees to conduct its standardization activities.  This publication identifies the service and product committees established by the Board of Directors and defines their scopes.

Committee(s): JC-COUN

Free download. Registration or login required.

Designator: PQFP-B#[#]_Ip27...

Item #: 11-1037 

Committee(s): JC-11.11

JEP95 Registrations Main Page

Free download. Registration or login required.

This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document.

Committee(s): JC-40.1

Free download. Registration or login required.

Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1

Item: 11-1030

Committee(s): JC-11.11

JEP95 Registrations Main Page

Free download. Registration or login required.

This document defines the LPDDR5/LPDDR5X standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5/LPDDR5X device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), and LPDDR4 (JESD209-4).

Committee(s): JC-42, JC-42.6

Available for purchase: $459.00 Add to Cart

Paying JEDEC Members may login for free access.

This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1.

Committee(s): JC-14, JC-14.1

Free download. Registration or login required.

This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212).

Committee(s): JC-42.3C

Free download. Registration or login required.

This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing.

Committee(s): JC-13, JC-13.5

Free download. Registration or login required.

This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence.

Committee(s): JC-14.3

Free download. Registration or login required.