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Release No. 19. Item 2065.26

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Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 5. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2276.05.

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Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 2. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. (This release is editorial changes only).

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Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 4. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01G. This is an editorial revision to the publication in January 2017.

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Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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Release No. 17

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Committee(s): JC-42, JC-45

JESD21-C Solid State Memory Documents Main Page

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Release No.9

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Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

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Release No.8

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Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

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Release No.13

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Committee(s): JC-42, JC-42.5

JESD21-C Solid State Memory Documents Main Page

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Release No.11

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Committee(s): JC-42.5

JESD21-C Solid State Memory Documents Main Page

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This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices.

The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

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Committee(s): JC-40, JC-40.1

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The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability.

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Committee(s): JC-14, JC-14.3

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Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser.  Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32

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Committee(s): JC-64.8

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This test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. It provides procedures for dip & look solderability testing of through hole, axial and surface mount devices and a surface mount process simulation test for surface mount packages. The purpose of this test method is to provide a means of determining the solderability of device package terminations that are intended to be joined to another surface using lead (Pb) containing or Pb-free solder for the attachment.

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Committee(s): JC-14.1

This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. This is a minor editorial revision to JESD22-A115A.

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Committee(s): JC-14, JC-14.1

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Release No. 16A

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Committee(s): JC-63

JESD21-C Solid State Memory Documents Main Page

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Signature Analysis is a method to reduce the number of comprehensive physical failure analyses by the application of statistical inference techniques. The purpose of this document is to promote a common definition of Signature Analysis by inference, using the same statistical techniques, and to recognize that it is formal means of doing failure analysis.

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Committee(s): JC-14.4

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Designator: N/A

Item #: 11.5-995

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Committee(s): JC-11, JC-11.5

JEP95 Registrations Main Page

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Designator: N/A

Item #: 11.5-1041

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Committee(s): JC-11, JC-11.5

JEP95 Registrations Main Page

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This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device.

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Committee(s): JC-42.4

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This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06.

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Committee(s): JC-42.4

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The purpose of these benchmarks is to provide a common set of high level functions which serve as vehicles for comparing the performance of gate arrays implemented in any technology using any internal structure. These benchmarks effectively provide an unbiased measure of gate array vendors' ability to implement a desired complex function on a particular gate array at a known level of performance.

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Committee(s): JC-44

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Semiconductor Power Control Modules (SPCM) are modules consisting of thyristors or transistors, or both, as the primary controlling elements. Methods of manufacture of semiconductor power control modules include the assembling of individual components and the use of semiconductor hybrids or monolithic processing technologies, or both.

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Committee(s): JC-22.2

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This standard describes SPI bus transactions intended to support Secure Flash operation on a serial memory device. The on-chip SFDP database described in JESD216 has been revised to include details about the secure transactions. This ballot does not describe the SFDP revisions or the secure packet structure.

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Committee(s): JC-42, JC-42.4

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Release No.16

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Committee(s): JC-42, JC-42.3

JESD21-C Solid State Memory Documents Main Page

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Salt atmosphere is a destructive, accelerated stress that simulates the effects of severe seacoast atmosphere on all exposed surfaces. Such stressing and post-stress testing determine the resistance of solid-state devices to corrosion and may be performed on commercial and industrial product in molded or hermetic packages.

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Committee(s): JC-14, JC-14.1

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Committee(s): JC-22.1

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-11

JEP95 Registrations Main Page

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Committee(s): JC-13

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