Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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DDR5 Clock Driver Definition (DDR5CKD01)Release Number: Version 1.1 |
JESD82-531A.01 | Feb 2024 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5, Free download. Registration or login required. |
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DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH, MICROELECTRONIC ASSEMBLY |
MO-358B | Jun 2024 |
Designator: XBNA-N#_I1p0_... Item No: 14-229 Free download. Registration or login required. |
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DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1 |
JESD82-521 | Dec 2021 |
This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K Committee(s): JC-40.4 Free download. Registration or login required. |
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DDR5 262 Pin SODIMM Connector Performance Standard |
PS-006B | Sep 2024 |
This standard defines the form, fit and function of SODIMM DDR5 connectors for modules supporting channels with transfer rates 6.4 GT/S and beyond. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide performance standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR5 connectors in client and server platforms. Item 14-226 Free download. Registration or login required. |
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DDR4 UDIMM Design Specification Annex D |
PRN14-NM1 | Feb 2014 |
Item 2231.09 Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR4 SDRAM STANDARD |
JESD79-4D | Jul 2021 |
This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H Committee(s): JC-42.3C Available for purchase: $284.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02) |
JESD82-31A.01 | Jan 2023 |
Terminology update. This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required. |
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DDR4 PROTOCOL CHECKS |
JEP175 | Jul 2017 |
The intended use of this document is for the validation and debug of DDR4 based designs. This document contains protocol checks, sometimes referred to as memory access rules or protocol violations. This document contains a list of checks that can be used during the verification or debug stages of development to check that accesses to a DDR4 DRAM adhere to JESD79-4B. These checks are derived from JESD79-4B. Item 31509. Committee(s): JC-40.5 Free download. Registration or login required. |
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DDR4 NVDIMM-P BUS PROTOCOL |
JESD304-4.01 | Jan 2021 |
This version is a minor editorial adding Annex B that was left out of the original publication October 2020. An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory. A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K. Committee(s): JC-45.6 Free download. Registration or login required. |
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DDR4 NVDIMM-N Design Standard |
JESD248A.01 | Apr 2023 |
Terminology update. This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash. Committee(s): JC-45.6 Available for purchase: $123.36 Add to Cart Paying JEDEC Members may login for free access. |
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DDR4 DIMM Product Label, Hybrid, Pre-Production, DDR4ERelease Number: 29 |
DIMM-LABEL4.19.4 | Aug 2019 |
This section covers DDR4 and DDR4E in both DRAM-only module types and Hybrid module types, as well as pre-production modules of both types. Item 2224.13A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR4 DATA BUFFER DEFINITION (DDR4DB02) |
JESD82-32A | Aug 2019 |
This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D *If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required. |
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DDR4 260 Pin SODIMM Connector Performance Standard |
PS-003A.01 | Jul 2016 |
This standard defines the form, fit and function of SODIMM DDR4 connectors for modules supporting channels with transfer rates as high as 3.2 GT/S. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR4 connectors in client and server platforms. Item 11.14-179E Patents(): FOXCONN US PATENT NO.: 5,882,211; 6,126,472; 6,113,398 Committee(s): JC-11.14 Free download. Registration or login required. |
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DDR3 Unbuffered Mini-DIMM, Annex B |
PRN11-NM2 | Jun 2011 |
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release JESD21C. Item 2201.10 Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR3 Unbuffered Mini-DIMM, Annex A |
PRN11-NM1 | Jun 2011 |
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of JESD21C. Item 2207.11 Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR3 Unbuffered MicroDIMM Design Specification, 214-Pin PC3-12800. Item 2031.04 |
MODULE4.20.17 | Mar 2007 |
Release No. 17 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR3 SDRAM STANDARD |
JESD79-3F | Jul 2012 |
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3 Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDR3 DIMM Product LabelRelease Number: 28 |
DIMM-LABEL4.19.3 | Dec 2018 |
This section covers DDR3 DIMM labels. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR3 DIMM Label |
PRN09-NM4 | Oct 2009 |
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 2099.01b Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR3 240-Pin Connector S-Parameters SpecificationThis document was originally published in Section 4.20.19 of JESD21C, it is now placed in its own section, Section 4.8, in 21C. A cross-reference to Section 4.8 has been placed in Section 4.20.19. |
MODULE4.8 | Jun 2011 |
Release No. 21 Committee(s): JC-45.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR2 Specific SDRAM Function |
SDRAM3.11.5.5 | Jul 2008 |
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION |
JEP179 | Jun 2006 |
The purpose of this document is to explain the meaning of SPD setting (JESD21 SPD section) for DDR2 SDRAM (JESD79-2) in normal and extended temperature operationy67. Committee(s): JC-42.3 Free download. Registration or login required. |
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DDR2 SDRAM STANDARD |
JESD79-2F | Nov 2009 |
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Free download. Registration or login required. |
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DDR2 DIMM Product LabelRelease Number: 28 |
DIMM-LABEL4.19.2 | Dec 2018 |
This section covers DDR2 DIMM labels. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD |
JEP152 | May 2007 |
This document is the work product of the JC-45.1 DDR2 DIMM Clock Skew Measurement task group.The purpose of this document is to define procedures to measure clock parameters on registered DIMMs using the DDR2 Clock Reference Board. It is NOT the intent of this document to set specification values or validation requirements. Free download. Registration or login required. |
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DDR Specific SDRAM Functions |
SDRAM3.11.5.2 | Jun 2003 |
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR DIMM Product LabelRelease Number: 28 |
DIMM-LABEL4.19-1 | Dec 2018 |
Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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CYCLED TEMPERATURE HUMIDITY-BIAS WITH SURFACE CONDENSATION LIFE TEST |
JESD22-A100E | Nov 2020 |
The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. The Cycled Temperature-Humidity-Bias Life Test is typically performed on cavity packages (e.g., MQUADs, lidded ceramic pin grid arrays, etc.) as an alternative to JESD22-A101 or JESD22-A110. Free download. Registration or login required. |
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CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS |
J-STD-046 | Jul 2016 |
This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. This standard establishes the requirements for timely customer notification of changes to electronic products and associated processes. This document replaces JESD46. Committee(s): JC-14.4 Free download. Registration or login required. |
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CUSTOMER NOTIFICATION PROCESS FOR DISASTERS |
JESD246A | Jan 2020 |
This standard establishes the requirements for timely notification to affected customers after a disaster has occurred at a supplier’s facility that will affect the committed delivery of product. This standard puts specific emphasis on notification, timing, and notification content which includes risk exposure, impact analysis, and recovery plans. This standard is applicable to suppliers of, and affected customers for, solid-state products and the constituent components used within. Committee(s): JC-14.4 Free download. Registration or login required. |
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CUSTOMER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY SOLID-STATE SUPPLIERSStatus: SupersededBy J-STD-046, July 2016 |
JESD46D | Dec 2011 |
This standard establishes procedures to notify customers of semiconductor product and process changes. Requirements include: documentation; procedures for classification, notification and customer response; content; and records. Documentation of a suppliers change notification system should set clear and understandable expectations for both the originators of the change and their end customers. |
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Customer Notification for Environmental Compliance Declaration Deviations |
JESD262 | Nov 2022 |
This standard is invoked when a supplier becomes aware that a product’s environmental compliance declaration they provided or made available to their customers had an error that might cause a customer to draw an incorrect conclusion about the compliance of the product to legal requirements. Committee(s): JC-14.4 Free download. Registration or login required. |
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CURRENT TIN WHISKERS THEORY AND MITIGATION PRACTICES GUIDELINEStatus: Reaffirmed February 2023 |
JP002 | Mar 2006 |
This document will provide insight into the theory behind tin whisker formation as it is known today and, based on this knowledge, potential mitigation practices that may delay the onset of, or prevent tin whisker formation. The potential effectiveness of various mitigation practices will also be briefly discussed. References behind each of the theories and mitigation practices are provided. Free download. Registration or login required. |
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COUNTERFEIT ELECTRONIC PARTS: NON-PROLIFERATION FOR MANUFACTURERS |
JESD243A | Jan 2021 |
This standard identifies the best commercial practices for mitigating and/or avoiding counterfeit products by all manufacturers of electronic parts including, but not limited to original component manufacturers (OCMs), authorized aftermarket manufacturers, and other companies that manufacture electronic parts under their own logo, name, or trademark. The types of product this standard applies to is limited to monolithic microcircuits, hybrid microcircuits and discrete semiconductor products. Committee(s): JC-13 Free download. Registration or login required. |
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COPY-EXACT PROCESS FOR MANUFACTURING |
JEP185 | Aug 2021 |
This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements. Committee(s): JC-14.3 Free download. Registration or login required. |
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COPLANARITY TEST FOR SURFACE-MOUNT SEMICONDUCTOR DEVICESStatus: Reaffirmed February 2023 |
JESD22-B108B | Sep 2010 |
The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used. Free download. Registration or login required. |
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CONSTANT-TEMPERATURE AGING METHOD TO CHARACTERIZE COPPER INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING |
JESD214.01 | Aug 2017 |
This document describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method may be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time. Committee(s): JC-14.2 Free download. Registration or login required. |
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CONFIGURATIONS FOR SOLID STATE MEMORIES:Status: Under RevisionSections in this document may be under revision at any time. |
JESD21-C | Jan 2003 |
This revision of JESD21 is substantially different from previous issues because it reflects advancement in semiconductor technology and computer design needs. A new class of memory devices, the multiport DRAM (MPDRAM) C also know as 'Video Ram' because of the most common application for the devices C is represented. A new family of SRAMs which addresses the increasing need for high speed is introduced. Additional families of devices in the SOJ and Zip packages are included. The material in this revision is organized primarily by function (ROM, EPROM, SRAM, DRAM, etc.) rather than by technology and word length. Pinouts for SIMM and DIMM are included along with presence detect schemes. A current set of terms has also been included. JESD21-C is a compilation of all memory device standards that have been developed by the JC-42 Committee and approved by the JEDEC BoD from September 1989 to present. This latest issue has changed to a loose-leaf format and comes in a three-ring binder so that new drawings can be added without requiring a new publication. Time of publication of the material is identified by release number, i.e., if marked Release 8, this item was approved and released in 1998, if marked Release 13, this item was approved and released in 2003. Committee(s): JC-42 |
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CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERS:Status: ReaffirmedApril 1999, April 2002 (Original publication July 1965) |
JESD320-A | Dec 1992 |
This standard provides guidance for achieving equilibrium when measuring temperature sensitive static parameters of signal diodes. Formerly known as EIA-320-A. Committee(s): JC-22.4 Free download. Registration or login required. |
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Compression Attached Memory Module (CAMM2) Common Standard |
JESD318A Ver. 1.10 | Nov 2024 |
This standard defines the electrical and mechanical requirements for Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LP5 SDRAM CAMM2s). Committee(s): JC-45 Free download. Registration or login required. |
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COMPONENT PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS - SUPERSEDED BY EIA-671, November 1996.Status: Superseded |
JESD43 | Nov 1996 |
Committee(s): JC-14.4 Free download. Registration or login required. |
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COMPACT THERMAL MODEL OVERVIEW |
JESD15-1.01 | Mar 2023 |
Terminology update. This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. Free download. Registration or login required. |
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COMMON FLASH INTERFACE (CFI): |
JESD68.01 | Sep 2003 |
The Common Flash Interface (CFI) specification outlines a device and host system software interrogation handshake that allows specific software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specific flash families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. The changes for this minor revision are indicated in Annex A on page 11. Committee(s): JC-42.4 Free download. Registration or login required. |
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COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES: |
JEP137B | May 2004 |
This publication is a companion document to the Common Flash Interface (CFI) standard, JESD68, which outlines the device and host system software interrogation handshake. JEP137 documents ID Code assignments for: 1)) the Algorithm-specific Command Set and Control Interfaces and 2) the Device Interfaces. It is published as needed when additions are made to either of these lists of codes. To make a request for an ID Code please contact the JEDEC Office at (703)907-7558. Committee(s): JC-42.4 Free download. Registration or login required. |
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COLOR CODING OF DISCRETE SEMICONDUCTOR DEVICESStatus: Reaffirmed November 1999, September 2009 |
JESD236-C | Mar 1986 |
This standard details the methods to be followed if color coding is used to identify JEDEC-assigned type numbers or for cathode identification of discrete semiconductor devices. Formerly known as EIA-236-C and/or ANSI/EIA-236-C-1986 (1995). Committee(s): JC-10 Free download. Registration or login required. |
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CMOS SEMICUSTOM DESIGN GUIDELINES: |
JEP116 | Nov 1991 |
The design of ASIC circuits is becoming a significant part of system or product design, yet many problems continue to exist in current design practice. The guidelines in this document provide an explanation of common ASIC design problems and concerns and where possible offer solutions. Committee(s): JC-44 Free download. Registration or login required. |
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CLASSIFICATION OF PASSIVE AND SOLID STATE DEVICES FOR ASSEMBLY PROCESSES |
J-STD-075A | May 2018 |
This is a Joint Standard between ECIA, IPC, and JEDEC. The purpose of this specification is to establish an agreed to set of worst case solder assembly process conditions to which devices are evaluated. The generated PSL rating will convey the conditions to which a device can be safely attached to FR4 type or ceramic laminates using SMT reflow and solder wave/fountain soldering processes. It is important for device manufacturers (hereafter referred to as “suppliers”), users, and (PWB) assemblers to be highly familiar with this standard’s information and processes to insure optimal device quality and reliability. THIS DOCUMENT IS NOT AVAILABLE FOR FREE DOWNLOAD. However, this document is available to the JEDEC formulating Committee members on the JC-14 Resources tab on the Members' website. The lead organization is ECIA. Committee(s): JC-14 |
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CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION |
JEP156A | Mar 2018 |
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. Free download. Registration or login required. |
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CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS: |
JESD11 | Dec 1984 |
This standard indicates the procedures used to convert existing DIP and flat packages for digital parts (SSI & MSI) to chip carrier packages. Committee(s): JC-40.2 Free download. Registration or login required. |
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CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES |
JEP167A | Nov 2020 |
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Committee(s): JC-14.1 Free download. Registration or login required. |
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CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURESStatus: Reaffirmed September 2019 |
JEP153A | Mar 2014 |
This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions are being achieved and maintained during various test procedures. Free download. Registration or login required. |
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CERAMIC PACKAGE SPECIFICATION FOR MICROELECTRONIC PACKAGES - SUPERSEDED BY JESD9B, May 2011.Status: Rescinded, May 2011 |
JESD27 | Aug 1993 |
The intent of this standard is to be a guide in the manufacture and procurement of ceramic packages, especially for the hybrid industry. Manufacturers or ceramic packages and procuring activities for these packages will now be able to use this document as the means for agreement in the imposition of minimum requirements in qualification, screening, and quality conformance. Free download. Registration or login required. |
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Byte Wide SRAM |
SRAM3.7.5 | Apr 2003 |
Release No.12 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide SDRAM |
SDRAM3.11.3 | Jan 2004 |
Release No.13 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide ROM |
ROM3.2.1 | Dec 1992 |
Release No.2 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide PROM |
PROM3.3.2 | Dec 1993 |
Release No.1 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide MPDRAM |
MPDRAM3.10.2 | Jun 1997 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide EEPROM |
EEPROM3.5.1 | Aug 2005 |
Release No. 14 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide ECL SRAM |
SRAM3.7.6 | Jul 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide DRAM |
DRAM3.9.3 | Jun 1999 |
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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